Anti-fuse circuit and method of operation

Abstract

An anti-fuse useful in implementing redundancy in a memory utilizes a normal transistor characteristic that is generally considered undesirable in order to provide two easily detected states. The un-programmed state, which is the high impedance state, is achieved simply with a normal transistor in its non-conductive state. The programmed state, which is the low impedance state, is achieved by forcing a normal transistor to conduct current through its gate. This causes the gate dielectric to become permanently conductive. This programmed transistor then is conductive between its source and drain that is easily differentiated from the transistor that is held in its non-conductive state. The result is a fuse technology using an anti-fuse that provides for easily distinguishable programmed and un-programmed states achieved by electrical programming rather than by laser programming.

What is claimed is:  
     
       1. An anti-fuse circuit, comprising: 
       an anti-fuse transistor operable as a normal transistor in a un-programmed condition and operable as a degraded transistor in a programmed condition, wherein the programmed condition is characterized by the degraded transistor having a first permanently conductive gate dielectric portion between a gate and a source and a second permanently conductive gate dielectric portion between the gate and a drain; and  
       a sensing output, coupled to the anti-fuse transistor, for providing a first sensing output value during the un-programmed condition and a second sensing output value during the programmed condition.  
     
     
       2. The anti-fuse circuit of  claim 1 , further comprising: 
       anti-fuse enable circuitry, coupled to the anti-fuse transistor, for selectively coupling a supply voltage to the anti-fuse transistor.  
     
     
       3. The anti-fuse circuit of  claim 2 , wherein the anti-fuse transistor comprises a transistor having a dielectric breakdown voltage, and wherein the supply voltage exceeds the dielectric breakdown voltage by an amount sufficient to form the first and second permanently conductive gate dielectric portions. 
     
     
       4. A method of operating an anti-fuse circuit, comprising: 
       enabling anti-fuse enabling circuitry coupled to an anti-fuse transistor having a gate electrode, a gate dielectric, a first current electrode, and a second current electrode; and  
       forming a degraded transistor from the anti-fuse transistor, wherein forming comprises:  
       applying a first voltage differential, via the anti-fuse enabling circuitry, for a first time period, between the gate electrode and the first current electrode sufficient to cause a first portion of the gate dielectric to become permanently conductive; and  
       applying a second voltage differential, via the anti-fuse enabling circuitry, for a second time period, between the gate electrode and the second current electrode sufficient to cause a second portion of the gate dielectric to become permanently conductive.  
     
     
       5. The method of  claim 4 , wherein prior to enabling the anti-fuse enabling circuitry, the anti-fuse transistor is operable as a normal transistor in a un-programmed state. 
     
     
       6. The method of  claim 4 , wherein the degraded transistor has a conductive permanent conductive path between the first and second current electrodes. 
     
     
       7. The method of  claim 6  wherein the second current electrode is floating during the first time period, and the first current electrode is floating during the second time period. 
     
     
       8. An anti-fuse circuit, comprising: 
       an anti-fuse transistor having a gate electrode, a first current electrode and a second current electrode and capable of operating in a un-programmed state or a programmed state; and  
       anti-fuse enabling circuitry having a first terminal coupled to first current electrode, second terminal coupled to second current electrode, and a third terminal coupled to the gate electrode of the anti-fuse transistor, the anti-fuse enabling circuitry applying a first voltage differential between the gate electrode and the first current electrode and a second voltage differential between the gate electrode and the second current electrode of the anti-fuse transistor to form a degraded transistor having permanently conductive gate dielectric portions, the degraded transistor corresponding to the programmed state of the anti-fuse transistor.  
     
     
       9. The anti-fuse circuit of  claim 8 , further comprising: 
       a sensing output coupled to the first current electrode of the anti-fuse transistor, the sensing output providing a first output value when the anti-fuse transistor is operating in the un-programmed state and a second output value when the anti-fuse transistors is operating in the programmed state.  
     
     
       10. The anti-fuse circuit of  claim 9 , wherein the first current electrode of the anti-fuse transistor is coupled to a second voltage supply and the second current electrode of the anti-fuse transistor is coupled to a third voltage supply.