Inventor
SCHINELLA RICHARD
US17 patents
Patents
17 patentsUS6881664B2Apr 19, 2005
Process for planarizing upper surface of damascene wiring structure for integrated circuit structures
LSI LOGIC CORP75 citations98
US6566262B1May 20, 2003
Method for creating self-aligned alloy capping layers for copper interconnect structures
LSI LOGIC CORP83 citations97
US6499003B2Dec 24, 2002
Method and apparatus for application of proximity correction with unitary segmentation
LSI LOGIC CORP88 citations97
US6391795B1May 21, 2002
Low k dielectric composite layer for intergrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning
LSI LOGIC CORP53 citations96
US5663017ASep 2, 1997
Optical corrective techniques with reticle formation and reticle stitching to provide design flexibility
LSI LOGIC CORP78 citations95
US6730588B1May 4, 2004
Method of forming SiGe gate electrode
LSI LOGIC CORP33 citations92
US6532585B1Mar 11, 2003
Method and apparatus for application of proximity correction with relative segmentation
LSI LOGIC CORP15 citations92
US6503840B2Jan 7, 2003
Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning
LSI LOGIC CORP40 citations92
US6175953B1Jan 16, 2001
Method and apparatus for general systematic application of proximity correction
LSI LOGIC CORP29 citations92
US5895261AApr 20, 1999
Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench
LSI LOGIC CORP32 citations92
US5670425ASep 23, 1997
Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench
LSI LOGIC CORP41 citations92
US6800940B2Oct 5, 2004
Low k dielectric composite layer for integrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning
LSI LOGIC CORP12 citations74
US6673498B1Jan 6, 2004
Method for reticle formation utilizing metal vaporization
LSI LOGIC CORP7 citations74
US6174630B1Jan 16, 2001
Method of proximity correction with relative segmentation
LSI LOGIC CORP12 citations73
US6743474B1Jun 1, 2004
Method for growing thin films
LSI LOGIC CORP2 citations63
US6747358B1Jun 8, 2004
Self-aligned alloy capping layers for copper interconnect structures
LSI LOGIC CORP2 citations62
US7081296B2Jul 25, 2006
Method for growing thin films
LSI LOGIC CORP0 citations52