Inventor
DODD JAMES M
US39 patents
⚠️ This page may combine multiple inventors who share the name “DODD JAMES M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
38 patentsUS7024518B2Apr 4, 2006
Dual-port buffer-to-memory interface
INTEL CORP151 citations99
US6795899B2Sep 21, 2004
Memory system with burst length shorter than prefetch length
INTEL CORP208 citations99
US6742098B1May 25, 2004
Dual-port buffer-to-memory interface
INTEL CORP445 citations99
US6618791B1Sep 9, 2003
System and method for controlling power states of a memory device via detection of a chip select signal
INTEL CORP198 citations99
US6493250B2Dec 10, 2002
Multi-tier point-to-point buffered memory interface
INTEL CORP223 citations99
US6862653B1Mar 1, 2005
System and method for controlling data flow direction in a memory system
INTEL CORP94 citations98
US6530006B1Mar 4, 2003
System and method for providing reliable transmission in a buffered memory system
INTEL CORP112 citations98
US6449213B1Sep 10, 2002
Memory interface having source-synchronous command/address signaling
INTEL CORP115 citations98
US6981089B2Dec 27, 2005
Memory bus termination with memory unit having termination control
INTEL CORP111 citations97
US6639820B1Oct 28, 2003
Memory buffer arrangement
INTEL CORP119 citations97
US6507530B1Jan 14, 2003
Weighted throttling mechanism with rank based throttling for a memory system
INTEL CORP77 citations97
US6553449B1Apr 22, 2003
System and method for providing concurrent row and column commands
INTEL CORP57 citations96
US7120765B2Oct 10, 2006
Memory transaction ordering
INTEL CORP25 citations93
US6772352B1Aug 3, 2004
Method and apparatus for reducing the rate of commands being issued if the rate exceeds a threshold which is based upon a temperature curve
INTEL CORP52 citations93
US6801459B2Oct 5, 2004
Obtaining data mask mapping information
INTEL CORP17 citations92
US6781911B2Aug 24, 2004
Early power-down digital memory device and method
INTEL CORP39 citations92
US6725349B2Apr 20, 2004
Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory
INTEL CORP34 citations92
US6505282B1Jan 7, 2003
Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristics
INTEL CORP43 citations92
US6212589B1Apr 3, 2001
System resource arbitration mechanism for a host bridge
INTEL CORP33 citations92
US5894567AApr 13, 1999
Mechanism for enabling multi-bit counter values to reliably cross between clocking domains
INTEL CORP23 citations92
US5640519AJun 17, 1997
Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme
INTEL CORP21 citations92
US5603010AFeb 11, 1997
Performing speculative system memory reads prior to decoding device code
INTEL CORP32 citations92
US6952745B1Oct 4, 2005
Device and method for maximizing performance on a memory interface with a variable number of channels
INTEL CORP33 citations91
US6766385B2Jul 20, 2004
Device and method for maximizing performance on a memory interface with a variable number of channels
INTEL CORP26 citations91
US7076617B2Jul 11, 2006
Adaptive page management
INTEL CORP11 citations84
US7000133B2Feb 14, 2006
Method and apparatus for controlling power states in a memory device utilizing state information
INTEL CORP12 citations84
US6957307B2Oct 18, 2005
Mapping data masks in hardware by controller programming
INTEL CORP14 citations84
US6442632B1Aug 27, 2002
System resource arbitration mechanism for a host bridge
INTEL CORP18 citations83
US7469316B2Dec 23, 2008
Buffered writes and memory page control
INTEL CORP8 citations74
US7159066B2Jan 2, 2007
Precharge suggestion
INTEL CORP8 citations74
US7404047B2Jul 22, 2008
Method and apparatus to improve multi-CPU system performance for accesses to memory
INTEL CORP7 citations73
US6952367B2Oct 4, 2005
Obtaining data mask mapping information
INTEL CORP6 citations73
US6148380ANov 14, 2000
Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
INTEL CORP13 citations73
US6934823B2Aug 23, 2005
Method and apparatus for handling memory read return data from different time domains
INTEL CORP4 citations63
US6535956B1Mar 18, 2003
Method and apparatus for automatically detecting whether a board level cache is implemented with Mcache
INTEL CORP2 citations63
US5898856AApr 27, 1999
Method and apparatus for automatically detecting a selected cache type
INTEL CORP3 citations63
US6925013B2Aug 2, 2005
Obtaining data mask mapping information
INTEL CORP0 citations52
US6888777B2May 3, 2005
Address decode
INTEL CORP0 citations51