Performing speculative system memory reads prior to decoding device code

Abstract

A method of improving computer system performance during memory reads. Prior art computer systems experience a considerable time penalty during microprocessor reads from system memory. This time penalty is mitigated by the method of the present invention, wherein data is speculatively retrieved from system memory upon receipt of a microprocessor read request. A microprocessor initiates a read request which is decoded by a memory controller. Before the decoding has completed, the memory controller speculatively begins to retrieve data from the system memory device. Thus if the decode step determines that the requested data is in system memory, the time required to retrieve the data is decreased.

What is claimed is: 
     
       1. A method of improving computer system performance during memory reads, the method comprising the steps of: (A) receiving a read request specifying a first memory source and a first address within said first memory source from which requested data is to be read;   (B) decoding said read request to identify a device corresponding to said first memory source; and   (C) speculatively initiating a fetch of data from a system memory using said first address, before step (B) has been completed.   
     
     
       2. The method of claim 1, wherein said system memory comprises dynamic random access memory (DRAM). 
     
     
       3. The method of claim 1, further comprising the steps of (D) finishing said decoding of said read request in step (B), and   (E) aborting step (C) if step (D) determines that said device corresponding to said first memory source is not said system memory.   
     
     
       4. The method of claim 3, wherein said read request is asserted by a host, and wherein step (E) further comprises the step of returning said data to said host if step (D) identifies said device corresponding to said first memory source as said system memory.   
     
     
       5. The method of claim 4, wherein said host is a microprocessor, and wherein said read request is issued using microprocessor read timings. 
     
     
       6. A method of automatically performing a read operation, comprising the steps of: (A) receiving a read command from a host specifying a location-of first data by including first address signals and first device signals;   (B ) decoding said first device signals to identify a first device containing said first data;   (C) speculatively initiating a fetch of data from system memory before step (B) has been completed, wherein said data corresponds to said first address signals;   (D) completing said decoding of said first device signals in step (B); and   (E) returning said data to said host in response to said read command if step (D) identifies said first device as said system memory.   
     
     
       7. The method of claim 6, wherein said system memory further comprises dynamic random access memory (DRAM). 
     
     
       8. The method of claim 6, wherein step (E) further comprises the step of: aborting step (C) if step (D) determines said first device is not said system memory.   
     
     
       9. The method of claim 6, wherein said host is a microprocessor, and wherein said read command is issued by said host according to microprocessor read timings. 
     
     
       10. A memory controller, comprising: (A) speculative read control circuitry that receives a read command from a host that includes an address and a device code, and wherein said speculative read control circuitry speculatively initiates a fetch of data from a system memory device using said address of said read command immediately upon receiving said read command and before said device code has been decoded; and   (B ) decode circuitry that decodes said read command to identify a memory device that is associated with said device code.   
     
     
       11. The memory controller of claim 10, wherein said speculative read control circuitry further comprises a state machine. 
     
     
       12. A computer system, comprising: a host;   a system memory device;   a memory controller, coupled to said host and said system memory device, said memory controller further comprising (A) speculative read control circuitry that receives a read command from said host, wherein said read command includes an address and a device code, and wherein said speculative read control circuitry speculatively initiates a fetch of data from said system memory device using said address of said read command immediately upon receiving said read command and before said device code has been decoded; and   (B) decode circuitry that decodes said read command to identify a memory device that is associated with said device code.     
     
     
       13. The computer system of claim 12, wherein said speculative read control circuitry further comprises a state machine. 
     
     
       14. The computer system of claim 12, wherein said system memory device comprises dynamic random access memory (DRAM). 
     
     
       15. The memory controller of claim 10, wherein said decode circuitry further comprises circuitry that asserts an abort signal to said speculative read control circuitry if, upon completion of decoding said read command, said decode circuitry determines that said memory device identified is not said system memory device.   
     
     
       16. The computer system of claim 12, wherein said decode circuitry further comprises circuitry that asserts an abort signal to said speculative read control circuitry if, upon completion of decoding said read command, said decode circuitry determines that said memory device identified is not said system memory device.   
     
     
       17. A memory controller, comprising: (A) speculative read control means for receiving a read command from a host that includes an address and a device code, and speculatively initiating a fetch of data from a system memory device using said address of said read command immediately upon receiving said read command and before said device code has been decoded; and   (B) decoding means for decoding said read command to identify a memory device that is associated with said device code.   
     
     
       18. The memory controller of device 17, wherein said decoding means further comprises means for asserting an abort signal to said speculative read control means if, upon completion of decoding said read command, said decoding means determines that said memory device identified is not said system memory device.