Inventor · disambiguated record
James M. Dodd
Also filed as: DODD JAMES M · DODD JAMES MICHAEL
40 granted patents·1 pending application·2,400 citations·filing 1995–2008
98Inventor score
Top patents by PatentIndex Score
41 records- 0199US6742098B1Dual-port buffer-to-memory interfaceINTEL CORP·Filed 2000·Granted May 25, 2004·445 cites·20 claims
- 0298US6795899B2Memory system with burst length shorter than prefetch lengthINTEL CORP·Filed 2002·Granted Sep 21, 2004·208 cites·35 claims
- 0398US6618791B1System and method for controlling power states of a memory device via detection of a chip select signalINTEL CORP·Filed 2000·Granted Sep 9, 2003·198 cites·14 claims
- 0498US6493250B2Multi-tier point-to-point buffered memory interfaceINTEL CORP·Filed 2000·Granted Dec 10, 2002·223 cites·24 claims
- 0597US7024518B2Dual-port buffer-to-memory interfaceINTEL CORP·Filed 2002·Granted Apr 4, 2006·151 cites·24 claims
- 0696US6639820B1Memory buffer arrangementINTEL CORP·Filed 2002·Granted Oct 28, 2003·119 cites·27 claims
- 0796US6449213B1Memory interface having source-synchronous command/address signalingINTEL CORP·Filed 2000·Granted Sep 10, 2002·115 cites·23 claims
- 0895US6981089B2Memory bus termination with memory unit having termination controlINTEL CORP·Filed 2001·Granted Dec 27, 2005·111 cites·28 claims
- 0995US6530006B1System and method for providing reliable transmission in a buffered memory systemINTEL CORP·Filed 2000·Granted Mar 4, 2003·112 cites·19 claims
- 1094US6862653B1System and method for controlling data flow direction in a memory systemINTEL CORP·Filed 2000·Granted Mar 1, 2005·94 cites·25 claims
- 1192US6507530B1Weighted throttling mechanism with rank based throttling for a memory systemINTEL CORP·Filed 2001·Granted Jan 14, 2003·77 cites·29 claims
- 1289US6553449B1System and method for providing concurrent row and column commandsINTEL CORP·Filed 2000·Granted Apr 22, 2003·57 cites·18 claims
- 1388US6772352B1Method and apparatus for reducing the rate of commands being issued if the rate exceeds a threshold which is based upon a temperature curveINTEL CORP·Filed 2000·Granted Aug 3, 2004·52 cites·33 claims
- 1485US6952745B1Device and method for maximizing performance on a memory interface with a variable number of channelsINTEL CORP·Filed 2004·Granted Oct 4, 2005·33 cites·11 claims
- 1585US6781911B2Early power-down digital memory device and methodINTEL CORP·Filed 2002·Granted Aug 24, 2004·39 cites·22 claims
- 1683US6725349B2Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memoryINTEL CORP·Filed 2003·Granted Apr 20, 2004·34 cites·12 claims
- 1782US6766385B2Device and method for maximizing performance on a memory interface with a variable number of channelsINTEL CORP·Filed 2002·Granted Jul 20, 2004·26 cites·17 claims
- 1879US7120765B2Memory transaction orderingINTEL CORP·Filed 2002·Granted Oct 10, 2006·25 cites·24 claims
- 1976US6801459B2Obtaining data mask mapping informationINTEL CORP·Filed 2002·Granted Oct 5, 2004·17 cites·12 claims
- 2073US6442632B1System resource arbitration mechanism for a host bridgeINTEL CORP·Filed 2000·Granted Aug 27, 2002·18 cites·7 claims
- 2169US6957307B2Mapping data masks in hardware by controller programmingINTEL CORP·Filed 2002·Granted Oct 18, 2005·14 cites·17 claims
- 2267US7076617B2Adaptive page managementINTEL CORP·Filed 2003·Granted Jul 11, 2006·11 cites·23 claims
- 2367US7000133B2Method and apparatus for controlling power states in a memory device utilizing state informationINTEL CORP·Filed 2002·Granted Feb 14, 2006·12 cites·25 claims
- 2464US6505282B1Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristicsINTEL CORP·Filed 1997·Granted Jan 7, 2003·43 cites·18 claims
- 2562US7469316B2Buffered writes and memory page controlINTEL CORP·Filed 2003·Granted Dec 23, 2008·8 cites·29 claims
- 2662US7159066B2Precharge suggestionINTEL CORP·Filed 2002·Granted Jan 2, 2007·8 cites·32 claims
- 2762US6952367B2Obtaining data mask mapping informationINTEL CORP·Filed 2003·Granted Oct 4, 2005·6 cites·16 claims
- 2860US7404047B2Method and apparatus to improve multi-CPU system performance for accesses to memoryINTEL CORP·Filed 2003·Granted Jul 22, 2008·7 cites·12 claims
- 2958US6212589B1System resource arbitration mechanism for a host bridgeINTEL CORP·Filed 1997·Granted Apr 3, 2001·33 cites·21 claims
- 3057US5603010APerforming speculative system memory reads prior to decoding device codeINTEL CORP·Filed 1995·Granted Feb 11, 1997·32 cites·18 claims
- 3155US6934823B2Method and apparatus for handling memory read return data from different time domainsINTEL CORP·Filed 2001·Granted Aug 23, 2005·4 cites·20 claims
- 3253US7858878B2Flush mount-corner mount gang boxHONEYWELL INT INC·Filed 2008·Granted Dec 28, 2010·5 cites·18 claims
- 3350US5894567AMechanism for enabling multi-bit counter values to reliably cross between clocking domainsINTEL CORP·Filed 1995·Granted Apr 13, 1999·23 cites·16 claims
- 3448US6925013B2Obtaining data mask mapping informationINTEL CORP·Filed 2004·Granted Aug 2, 2005·0 cites·9 claims
- 3548US5640519AMethod and apparatus to improve latency experienced by an agent under a round robin arbitration schemeINTEL CORP·Filed 1995·Granted Jun 17, 1997·21 cites·24 claims
- 3644US6888777B2Address decodeINTEL CORP·Filed 2002·Granted May 3, 2005·0 cites·39 claims
- 3740US7523230B1Device and method for maximizing performance on a memory interface with a variable number of channelsDODD JAMES M·Filed 2005·Granted Apr 21, 2009·1 cites·8 claims
- 3840US6148380AMethod and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system busINTEL CORP·Filed 1997·Granted Nov 14, 2000·13 cites·3 claims
- 3932US6535956B1Method and apparatus for automatically detecting whether a board level cache is implemented with McacheINTEL CORP·Filed 1998·Granted Mar 18, 2003·2 cites·24 claims
- 4032US5898856AMethod and apparatus for automatically detecting a selected cache typeINTEL CORP·Filed 1995·Granted Apr 27, 1999·3 cites·13 claims
- 4131US2004015645A1System, apparatus, and method for a flexible DRAM architectureFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →