Inventor

ANAND DARREN L

US42 patents

⚠️ This page may combine multiple inventors who share the name “ANAND DARREN L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANAND DARREN L

IBM

Method of electrically blowing fuses under control of an on-chip tester interface apparatus

Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox

Method and apparatus for preventing postamble corruption within a memory system

Fuse latch with compensated programmable resistive trip point

System and method for providing DRAM device-level repair via address remappings external to the device

Apparatus and method for improving sensing margin of electrically programmable fuses

Electronic fuse blow mimic and methods for adjusting electronic fuse blow

Automatic bit fail mapping for embedded memories with clock multipliers

Refresh hidden eDRAM memory

Regulating electrical fuse programming current

System and method for differential eFUSE sensing without reference fuses

Circuitry and method for programming an electrically programmable fuse

Method for reduced electrical fusing time

System for acquiring device parameters

Method and circuit for precise timing of signals in an embedded DRAM array

Flexible multibanking interface for embedded memory applications

Column redundancy system and method for embedded DRAM devices with multibanking capability

Latching current sensing amplifier for memory array

Design structure for improving sensing margin of electrically programmable fuses

System and method for indicating status of an on-chip power supply system

System and method for implementing self-timed decoded data paths in integrated circuits

Modular DLL architecture for generating multiple timings

System and method for direct write to dynamic random access memory (DRAM) using PFET bit-switch

Diagnostic method and apparatus for non-destructively observing latch data

Delay circuit with delay equal to percentage of input pulse width

Method for separating shift and scan paths on scan-only, single port LSSD latches

Method for improving sensing margin of electrically programmable fuses

Diagnostic method and apparatus for non-destructively observing latch data

Diagnostic method and apparatus for non-destructively observing latch data

GLOBALFOUNDRIES INC

Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing

Voltage-aware adaptive static random access memory (SRAM) write assist circuit

Robust and error free physical unclonable function using twin-cell charge trap transistor memory

Parallel programming of one time programmable memory array for reduced test time

Program and erase memory structures

Latching current sensing amplifier for memory array

Margin test for multiple-time programmable memory (MTPM) with split wordlines

Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing

ANAND DARREN L

Fusebay controller structure, system, and method

Reference generator with programmable M and B parameters and methods of use

Multi-bank random access memory structure with global and local signal buffering for improved performance

GLOBALFOUNDRIES US INC

Charge trap memory devices

MARVELL INT LTD

Selection circuit