Inventor

HUOTT WILLIAM V

US73 patents

⚠️ This page may combine multiple inventors who share the name “HUOTT WILLIAM V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUOTT WILLIAM V

IBM

Method for IC fault analysis using programmable built-in self test and optical emission

Built in self test circuit for measuring total timing uncertainty in a digital data path

Array self repair using built-in self test techniques

Global transition scan based AC method

Multiple input shift register (MISR) signatures used on architected registers to detect interim functional errors on instruction stream test

Isolation/removal of faults during LBIST testing

Programmable delay clock chopper/stretcher with fast recovery

Efficient method of test and soft repair of SRAM with redundancy

Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection

Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection

Partitioned pseudo-random logic test for improved manufacturability of semiconductor chips

Programmable built-in self test method and controller for arrays

Merged MISR and output register without performance impact for circuits under test

Methods and apparatus for testing a scan chain to isolate defects

Automatic timing analyzer

Built-in testing of unused element on chip

Efficient memory product for test and soft repair of SRAM with redundancy

Self test apparatus for identifying partially defective memory

Eight transistor SRAM cell with improved stability requiring only one word line

Merged MISR and output register without performance impact for circuits under test

Eight transistor SRAM cell with improved stability requiring only one word line

Multi-match error detection in content addressable memory testing

Mitigation of EMI/ESD-caused transmission errors on an electronic circuit

Methods and apparatus for testing a scan chain to isolate defects

Method and system for at speed diagnostics and bit fail mapping

Shift register with opposite shift data and shift clock directions

Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection

Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancy

Method and apparatus for facilitating random pattern testing of logic structures

System testing using partitioned and controlled noise

SRAM margin recovery during burn-in

Managing chip testing data

High-speed level sensitive scan design test scheme with pipelined test clocks

System and method for local generation of a ratio clock

Implementing dynamic SEU detection and correction method and circuit

Granular variable impedance tuning

Implementing SEU detection method and circuit

Built-in testing of unused element on chip

Method and apparatus for delaying ABIST start

Error protection for integrated circuits

Placement of storage cells on an integrated circuit

Shared error protection for register banks

Method for self-correcting cache using line delete, data logging, and fuse repair correction

Self test method and apparatus for identifying partially defective memory

Method to limit the time a semiconductor device operates above a maximum operating voltage

Microchip level shared array repair

SRAM margin recovery during burn-in

SRAM margin recovery during burn-in

Mitigation of side effects of simultaneous switching of input/output (I/O data signals

DUFFY KEVIN J

Memory testing system