Inventor

WONG SHYH-CHYI

TW63 patents

⚠️ This page may combine multiple inventors who share the name “WONG SHYH-CHYI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WONG SHYH-CHYI

TAIWAN SEMICONDUCTOR MFG

Structure to reduce the degradation of the Q value of an inductor caused by via resistance

Method of forming crown-type MIM capacitor integrated with the CU damascene process

OTP (open trigger path) latchup scheme using buried-diode for sub-quarter micron transistors

Body contact for a MOSFET device fabricated in an SOI layer

Method of making a body contact for a MOSFET device fabricated in an SOI layer

RF seal ring structure

High density stacked mim capacitor structure

High density stacked MIM capacitor structure

CMOS FET with P-well with P- type halo under drain and counterdoped N- halo under source region

OTP (open trigger path) latchup scheme using triple and buried well for sub-quarter micron transistors

Dynamic threshold MOSFET using accumulated base BJT level shifter for low voltage sub-quarter micron transistor

Drain and source engineering for ESD-protection transistors

Cascode MOS current mirror with lateral bipolar junction transistor to enhance ouput signal swing

Method for fabricating an accumulated-base bipolar junction transistor

Method of making NMOS and PMOS LDD transistors utilizing thinned sidewall spacers

High fMAX deep submicron MOSFET

Self-aligned process for a stacked gate RF MOSFET device

High Q inductor with Cu damascene via/trench etching simultaneous module

Gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology

Chain gate MOS structure

Method of forming gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology

Self-aligned process for a stacked gate RF MOSFET device

Method of forming resistors

Method of making a stack-polysilicon capacitor-coupled dual power supply input/output protection circuit

Layout pattern for improved MOS device matching

Layout pattern for improved MOS device matching

CMOS OP-AMP circuit using BJT as input stage

Method of using an insulator spacer to form a narrow base width lateral bipolar junction transistor

Method for fabricating narrow base width lateral bipolar junction transistor, on SOI layer

WINBOND ELECTRONICS CORP

Dual-node capacitor coupled MOSFET for improving ESD performance

Early trigger of ESD protection device by a current spike generator

Buried guard rings for CMOS device

Charge-pumping circuits for a low-supply voltage

Buried shallow trench isolation and method for forming the same

Buried shallow trench isolation and method for forming the same

Early trigger of ESD protection device by an oscillation circuit

Charge pump circuits for low supply voltages

Dual-node capacitor coupled MOSFET for improving ESD performance

Electrostatic discharge protection circuit triggered by PNP bipolar action

Method for modeling an integrated circuit including a DRAM cell

Buried shallow trench isolation and method for forming the same

Buried guard rings and method for forming the same

RICHWAVE TECHNOLOGY CORP

Low noise and high gain low noise amplifier

Single-ended input to differential output low noise amplifier with a cascode topology

Adaptive bias circuit and system thereof

High-efficiency single to differential amplifier

Linearized bias circuit with adaptation

HUANG CHIH-WEI

Piezoresistive type Z-axis accelerometer

STEINBACH ECKEHARD GOETZ

Error resilient video transmission using instantaneous receiver feedback and channel quality adaptive packet retransmission

WINDBOND ELECTRONICS CORP

Soi structure with a body contact