Dual-node capacitor coupled MOSFET for improving ESD performance

Abstract

A dual-node capacitor coupling technique is used to lower the trigger voltage and to improve the uniform turn-on of a multi-finger MOSFET transistor. Preferably, each MOSFET is an NMOS device. Specifically, each NMOS device includes a capacitor that is connected between the gate of the NMOS device and the pad terminal. A first resistor is connected between the gate and the p-well, while a second resistor is connected between the p-well and the grounded source. For a positive ESD pulse to VSS, the p-well is pulled up to approximately 0.7 V during the initial ESD event, such that the source junction is forward biased and that the trigger voltage of the NMOS device is lowered. At the same time the gate voltage is coupled within the range of approximately 1 to 2 V to promote the uniform turn on of the gate fingers of the NMOS devices during the initial ESD event.

What is claimed is:  
     
       1. An ESD protection circuit for lowering the trigger voltage and improving the turn-on consistency of a MOSFET device, comprising: 
       a MOSFET device having a source, a drain, a gate and a bulk;  
       a capacitor connected the gate of said MOSFET and a pad terminal;  
       a first resistor connected between the gate and the bulk of said MOSFET; and  
       a second resistor connected between the bulk and a power bus.  
     
     
       2. The circuit of  claim 1 , wherein said source is connected to said power bus. 
     
     
       3. The circuit of  claim 1 , wherein said MOSFET is a PMOSFET. 
     
     
       4. The circuit of  claim 3 , wherein said power bus is VDD. 
     
     
       5. The circuit of  claim 1 , further comprising multiple MOSFET devices connected in parallel, wherein all gates of said multiple MOSFET devices are electrically connected together. 
     
     
       6. The circuit of  claim 5 , wherein at least two drains of said multiple MOSFET devices are electrically connected together. 
     
     
       7. The circuit of  claim 5 , wherein at least two MOSFET devices share a common drain diffusion region. 
     
     
       8. The circuit of  claim 5 , wherein at least two sources of said multiple MOSFET devices are electrically connected together. 
     
     
       9. The circuit of  claim 5 , wherein at least two MOSFET devices share a common source diffusion region. 
     
     
       10. The circuit of  claim 5 , wherein said multiple MOSFET devices form a multi-finger structure. 
     
     
       11. The circuit of  claim 1 , wherein said drain is connected between said pad and a buffer. 
     
     
       12. The circuit of  claim 11 , wherein said bulk is a p-well, said p-well having a voltage potential of approximately 0.7 V, and said gate has a voltage potential approximately in the range of 1.0 to 2.0 V during as ESD event. 
     
     
       13. The circuit of  claim 1 , wherein said MOSFET is an NMOSFET. 
     
     
       14. The circuit of  claim 13 , wherein said power bus is a GND. 
     
     
       15. The circuit of  claim 1 , further comprising a third resistor connected between said pad terminal and a buffer. 
     
     
       16. The circuit of  claim 15 , further comprising a second MOSFET coupled between said buffer and said power bus. 
     
     
       17. An ESD protection circuit for lowering the trigger voltage and improving the turn-on consistency of a MOSFET device, comprising: 
       a MOSFET device having a source, a drain, a gate and a bulk;  
       a capacitor connected between the gate of said MOSFET and a first power bus;  
       a first resistor connected between the gate and the bulk of said MOSFET; and  
       second resistor connected between the bulk and a second power bus.  
     
     
       18. The circuit of  claim 17 , wherein said first power bus is a VDD bus and said second power bus is a VSS bus. 
     
     
       19. The circuit of  claim 17 , wherein said first power bus is a VDD bus and said second power bus is GND. 
     
     
       20. The circuit of  claim 17 , wherein said drain of said MOSFET is connected to said first power bus and said source of said MOSFET is connected to said second power bus. 
     
     
       21. The circuit of  claim 17 , wherein said second resistor is in series with said first resistor. 
     
     
       22. An ESD protection structure, comprising: 
       a MOSFET device comprising a source, a drain, a gate and a body;  
       a capacitor coupled between said gate and said drain;  
       a first resistor coupled between said gate and said body; and  
       a second resistor coupled between said body and said source.  
     
     
       23. The circuit of  claim 22 , wherein said source is connected to a power bus. 
     
     
       24. The circuit of  claim 23 , wherein said power bus is a GND. 
     
     
       25. The circuit of  claim 22 , wherein said MOSFET is a PMOSFET. 
     
     
       26. The circuit of  claim 22 , further comprising multiple MOSFET devices connected in parallel, wherein all gates of said multiple MOSFET devices are electrically connected together. 
     
     
       27. The circuit of  claim 26 , wherein at least two drains of said multiple MOSFET devices are electrically connected together. 
     
     
       28. The circuit of  claim 26 , wherein at least two MOSFET device share a common drain diffusion region. 
     
     
       29. The circuit of  claim 26 , wherein at least two sources of said multiple MOSFET devices are electrically connected together. 
     
     
       30. The circuit of  claim 26 , wherein at least two MOSFET device share a common source diffusion region. 
     
     
       31. The circuit of  claim 26 , wherein said multiple MOSFET devices form a multi-finger structure. 
     
     
       32. The circuit of  claim 22 , wherein said drain is connected between a pad and a buffer. 
     
     
       33. The circuit of  claim 22 , wherein said MOSFET is an NMOSFET. 
     
     
       34. The circuit of  claim 22 , further comprising a third resistor connected between said drain and a buffer. 
     
     
       35. An ESD protection circuit for an integrated circuit, comprising: 
         a MOS transistor having a source node, a drain node, a gate node and a base node, wherein said gate node is coupled to a first node through a capacitor and is coupled to a second node through a first resistor, wherein said base node is coupled to the first node through said capacitor and is coupled to the second node through said first resistor, and wherein said first node is subject to electrostatic - discharge stress during an ESD event.   
     
     
       36. The circuit of  claim 35 , wherein said first node is coupled to said drain node. 
     
     
       37. The circuit of  claim 35 , wherein said first node is coupled to a signal pad. 
     
     
       38. The circuit of  claim 35 , wherein said first node is coupled to a first power bus. 
     
     
       39. The circuit of  claim 35 , wherein said second node is coupled to said source node. 
     
     
       40. The circuit of  claim 35 , wherein said second node is coupled to a second power bus. 
     
     
       41. The circuit of  claim 35 , wherein said MOS transistor is a NMOS transistor, said base node being a p- well, and said second node being coupled to VSS.   
     
     
       42. The circuit of  claim 35 , wherein said MOS transistor is a PMOS transistor, said base note being an n- well, and said second node being coupled to VDD.   
     
     
       43. The circuit of  claim 35 , wherein said MOS transistor is a multi- gate - finger MOS transistor.   
     
     
       44. The circuit of  claim 35  further comprising an electrically conducting element coupled between said gate node and said base node. 
     
     
       45. The circuit of  claim 44 , wherein said electrically conducting element is a second resistor. 
     
     
       46. An ESD protection circuit, comprising: 
         a MOS transistor having a source node, a drain node, a gate node, and a base node, wherein said gate node is coupled to a first node through a first impedance and is coupled to a second node through a second impedance, wherein said base node is coupled to the first node through said first impedance and is coupled to the second node through said second impedance, and wherein said first node is subject to electrostatic - discharge stress during an ESD event.   
     
     
       47. The circuit of  claim 46 , wherein said first impedance comprises a capacitive element. 
     
     
       48. The circuit of  claim 46 , wherein said first node is coupled to said drain node. 
     
     
       49. The circuit of  claim 46 , wherein said first node is coupled to a single pad. 
     
     
       50. The circuit of  claim 46 , wherein said first node is coupled to a first power bus. 
     
     
       51. The circuit of  claim 46 , wherein said second node is coupled to said source node. 
     
     
       52. The circuit of  claim 46 , wherein said second node is coupled a second power bus. 
     
     
       53. The circuit of  claim 46 , wherein said MOS transistor is a NMOS transistor, said base region being a p- well, and said second node being coupled to ground.   
     
     
       54. The circuit of  claim 46 , wherein said MOS transistor is a PMOS transistor, said base node being an n- well, and said second node being coupled to VDD.   
     
     
       55. The circuit of  claim 46 , wherein said MOS transistor is a multi- gate - finger MOS transistor.   
     
     
       56. The circuit of  claim 46 , further comprising an electrically conducting element coupled between said gate node and said base node. 
     
     
       57. The circuit of  claim 56 , wherein said electrically conducting element is a resistor.