Inventor · disambiguated record
Gary J. Nacer
Also filed as: NACER GARY · NACER GARY J
18 granted patents·3 pending applications·57 citations·filing 2003–2018
93Inventor score
Files withOPTIMUM SEMICONDUCTOR TECH INC18ASPEN ACQUISITION CORP1SANDBRIDGE TECHNOLOGIES INC1WANG SHENGHONG1
Top patents by PatentIndex Score
21 records- 0196US10339095B2Vector processor configured to operate on variable length vectors using digital signal processing instructionsOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted Jul 2, 2019·18 cites·22 claims
- 0289US9910824B2Vector processor configured to operate on variable length vectors using instructions to combine and split vectorsOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted Mar 6, 2018·4 cites·22 claims
- 0388US10169039B2Computer processor that implements pre-translation of virtual addressesOPTIMUM SEMICONDUCTOR TECH INC·Filed 2016·Granted Jan 1, 2019·5 cites·46 claims
- 0483US10908909B2Processor with mode supportOPTIMUM SEMICONDUCTOR TECH INC·Filed 2016·Granted Feb 2, 2021·4 cites·21 claims
- 0583US10824586B2Vector processor configured to operate on variable length vectors using one or more complex arithmetic instructionsOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted Nov 3, 2020·2 cites·42 claims
- 0682US11544214B2Monolithic vector processor configured to operate on variable length vectors using a vector length registerOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted Jan 3, 2023·2 cites·38 claims
- 0780US9792116B2Computer processor that implements pre-translation of virtual addresses with target registersOPTIMUM SEMICONDUCTOR TECH INC·Filed 2016·Granted Oct 17, 2017·2 cites·46 claims
- 0873US10339094B2Vector processor configured to operate on variable length vectors with asymmetric multi-threadingOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted Jul 2, 2019·1 cites·23 claims
- 0973US9558000B2Multithreading using an ordered list of hardware contextsOPTIMUM SEMICONDUCTOR TECH INC·Filed 2014·Granted Jan 31, 2017·3 cites·24 claims
- 1072US9940129B2Computer processor with register direct branches and employing an instruction preload structureOPTIMUM SEMICONDUCTOR TECH INC·Filed 2016·Granted Apr 10, 2018·1 cites·26 claims
- 1172US9766894B2Method and apparatus for enabling a processor to generate pipeline control signalsOPTIMUM SEMICONDUCTOR TECH INC·Filed 2014·Granted Sep 19, 2017·3 cites·26 claims
- 1271US8471597B2Power saving circuit using a clock buffer and multiple flip-flopsWANG SHENGHONG·Filed 2009·Granted Jun 25, 2013·7 cites·13 claims
- 1364US10719451B2Variable translation-lookaside buffer (TLB) indexingOPTIMUM SEMICONDUCTOR TECH INC·Filed 2018·Granted Jul 21, 2020·1 cites·19 claims
- 1460US10846259B2Vector processor to operate on variable length vectors with out-of-order executionOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted Nov 24, 2020·0 cites·63 claims
- 1559US10922267B2Vector processor to operate on variable length vectors using graphics processing instructionsOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted Feb 16, 2021·0 cites·14 claims
- 1659US2016224514A1Vector processor configured to operate on variable length vectors with register renamingOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Application pending·0 cites
- 1756US10514915B2Computer processor with address register fileOPTIMUM SEMICONDUCTOR TECH INC·Filed 2016·Granted Dec 24, 2019·0 cites·46 claims
- 1851US9766895B2Opportunity multithreading in a multithreaded processor with instruction chaining capabilityOPTIMUM SEMICONDUCTOR TECH INC·Filed 2014·Granted Sep 19, 2017·0 cites·22 claims
- 1951US7158583B2Multiple communication protocols with common sampling rateSANDBRIDGE TECHNOLOGIES INC·Filed 2003·Granted Jan 2, 2007·4 cites·8 claims
- 2044US2011241744A1Latch-based implementation of a register file for a multi-threaded processorASPEN ACQUISITION CORP·Filed 2009·Application pending·0 cites
- 2141US2018203703A1Implementation of register renaming, call-return prediction and prefetchOPTIMUM SEMICONDUCTOR TECH INC·Filed 2018·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →