Inventor

PAREKH KUNAL

US30 patents

⚠️ This page may combine multiple inventors who share the name “PAREKH KUNAL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAREKH KUNAL

MICRON TECHNOLOGY INC

Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells

Integrated circuits comprising interconnecting plugs

Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells

Semiconductor with through-substrate interconnect

Method of making a capacitor

Method of forming a cylindrical container stacked capacitor

Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances

Method of making a capacitor

Method of forming a capacitor

Method of making a concave capacitor

Method of forming a capacitor and a capacitor construction

Capacitor structure

Capacitor structure

Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances

Method of manufacturing sidewall spacers on a memory device, and device comprising same

Method of manufacturing sidewall spacers on a memory device, and device comprising same

Container capacitor

Methods for forming narrow vertical pillars and integrated circuit devices having the same

Methods for forming narrow vertical pillars and integrated circuit devices having the same

Stepped gate configuration for non-volatile memory

Method of forming a capacitor

Method of manufacturing sidewall spacers on a memory device, and device comprising same

Methods for forming narrow vertical pillars and integrated circuit devices having the same

Methods for forming narrow vertical pillars and integrated circuit devices having the same

Stepped gate configuration for non-volatile memory

Capacitor structure

Capacitor structure

Memory having buried digit lines and methods of making the same

PAREKH KUNAL

Method of forming a DRAM array of devices with vertically integrated recessed access device and digitline

Memory having buried digit lines and methods of making the same