Method of forming a capacitor and a capacitor construction
Abstract
The invention encompasses capacitor constructions. In one aspect, the invention includes a stacked capacitor construction comprising: a) a substrate; b) an electrically conductive runner provided on the substrate, the runner having an outer conductive surface; c) a node on the substrate adjacent the electrically conductive runner; d) an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node adjacent the conductive runner, the pillar having an outer surface; e) an electrically conductive storage node container layer in electrical connection with the pillar; f) a capacitor dielectric layer over the capacitor storage node layer; and g) an electrically conductive outer capacitor plate over the capacitor dielectric layer; and h) the pillar outer surface being elevationally inward of the runner outer surface.
Claims
exact text as granted — not AI-modifiedWe claim:
1. A stacked capacitor construction, comprising: a substrate; a pair of conductive runners on the substrate, the conductive runners having electrically conductive uppermost surfaces and being a first conductive runner and a second conductive runner; a first insulative cap over the uppermost surface of the first conductive runner, and a second insulative cap over the uppermost surface of the second conductive runner; a node on the substrate and positioned between the pair of runners; a conductive pillar between the conductive runners and electrically contacting the node; an insulating layer positioned over the conductive runners and having an opening therein, the insulating layer comprising a different material than the first and second insulative caps; a storage node layer within the opening and electrically contacting the conductive pillar, the storage node physically contacting both the first and second insulative caps; a dielectric layer proximate the storage node layer; and a conductive outer plate proximate the dielectric layer; and a recess extending downwardly into one of the insulative caps, the storage node layer extending downwardly into the recess.
2. The capacitor of claim 1 further comprising: first and second insulative sidewall spacers physically contacting sidewalls of the first and second conductive runners, respectively, the first and second insulative spacers comprising a different material than the insulating layer; and the storage node layer physically contacting at least one of the first insulative sidewall spacer or the second insulative sidewall spacer.
3. The capacitor of claim 2 wherein the storage node layer physically contacts both first insulative sidewall spacer and the second insulative sidewall spacer. the first and second insulative spacers comprising a different material than the insulating layer.
4. The stacked capacitor of claim 1 wherein the first and second insulative caps comprise Si 3 N 4 and the insulating layer comprises BPSG.
5. The stacked capacitor of claim 2 wherein the first and second insulative spacers comprise Si 3 N 4 , the first and second insulative caps comprise Si 3 N 4 , and the insulating layer comprises BPSG.Cited by (0)
No later patents cite this yet.
References (0)
No backward citations on record.