Inventor
MISTRY KAIZAD R
US14 patents
⚠️ This page may combine multiple inventors who share the name “MISTRY KAIZAD R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
9 patentsUS6885084B2Apr 26, 2005
Semiconductor transistor having a stressed channel
INTEL CORP159 citations99
US6861318B2Mar 1, 2005
Semiconductor transistor having a stressed channel
INTEL CORP165 citations99
US6621131B2Sep 16, 2003
Semiconductor transistor having a stressed channel
INTEL CORP534 citations99
US6956263B1Oct 18, 2005
Field effect transistor structure with self-aligned raised source/drain extensions
INTEL CORP43 citations92
US6716046B2Apr 6, 2004
Field effect transistor structure with self-aligned raised source/drain extensions
INTEL CORP27 citations92
US6693331B2Feb 17, 2004
Method of fabricating dual threshold voltage n-channel and p-channel MOSFETS with a single extra masked implant operation
INTEL CORP18 citations92
US6362034B1Mar 26, 2002
Method of forming MOSFET gate electrodes having reduced depletion region growth sensitivity to applied electric field
INTEL CORP28 citations91
US6803285B2Oct 12, 2004
Method of fabricating dual threshold voltage n-channel and p-channel mosfets with a single extra masked implant operation
INTEL CORP11 citations73
US9735270B2Aug 15, 2017
Semiconductor transistor having a stressed channel
INTEL CORP0 citations52
DIGITAL EQUIPMENT CORP
4 patentsUS5262344ANov 16, 1993
N-channel clamp for ESD protection in self-aligned silicided CMOS process
DIGITAL EQUIPMENT CORP60 citations95
US6078487AJun 20, 2000
Electro-static discharge protection device having a modulated control input terminal
DIGITAL EQUIPMENT CORP56 citations94
US5525829AJun 11, 1996
Field effect transistor with integrated schottky diode clamp
DIGITAL EQUIPMENT CORP24 citations92
US5021853AJun 4, 1991
N-channel clamp for ESD protection in self-aligned silicided CMOS process
DIGITAL EQUIPMENT CORP51 citations92