Inventor
ZARRINEH KAMRAN
US18 patents
⚠️ This page may combine multiple inventors who share the name “ZARRINEH KAMRAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SUN MICROSYSTEMS INC
11 patentsUS7178076B1Feb 13, 2007
Architecture of an efficient at-speed programmable memory built-in self test
SUN MICROSYSTEMS INC53 citations95
US6893154B2May 17, 2005
Integrated temperature sensor
SUN MICROSYSTEMS INC27 citations92
US6813201B2Nov 2, 2004
Automatic generation and validation of memory test models
SUN MICROSYSTEMS INC18 citations92
US6806698B2Oct 19, 2004
Quantifying a difference between nodal voltages
SUN MICROSYSTEMS INC28 citations92
US7206979B1Apr 17, 2007
Method and apparatus for at-speed diagnostics of embedded memories
SUN MICROSYSTEMS INC28 citations91
US6937958B2Aug 30, 2005
Controller for monitoring temperature
SUN MICROSYSTEMS INC22 citations91
US7260759B1Aug 21, 2007
Method and apparatus for an efficient memory built-in self test architecture for high performance microprocessors
SUN MICROSYSTEMS INC27 citations87
US7293199B1Nov 6, 2007
Method and apparatus for testing memories with different read/write protocols using the same programmable memory bist controller
SUN MICROSYSTEMS INC12 citations76
US6809557B2Oct 26, 2004
Increasing power supply noise rejection using linear voltage regulators in an on-chip temperature sensor
SUN MICROSYSTEMS INC7 citations74
US6605988B1Aug 12, 2003
Low voltage temperature-independent and temperature-dependent voltage generator
SUN MICROSYSTEMS INC11 citations73
US6700946B2Mar 2, 2004
System and method for automatic generation of an at-speed counter
SUN MICROSYSTEMS INC9 citations71
CADENCE DESIGN SYSTEMS INC
4 patentsUS7168005B2Jan 23, 2007
Programable multi-port memory BIST with compact microcode
CADENCE DESIGN SYSTEMS INC91 citations97
US6557127B1Apr 29, 2003
Method and apparatus for testing multi-port memories
CADENCE DESIGN SYSTEMS INC67 citations95
US6681350B2Jan 20, 2004
Method and apparatus for testing memory cells for data retention faults
CADENCE DESIGN SYSTEMS INC6 citations57
US7032144B2Apr 18, 2006
Method and apparatus for testing multi-port memories
CADENCE DESIGN SYSTEMS INC1 citations51