Method and apparatus for testing multi-port memories

Abstract

A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not directly accessible.

1. A method for testing a multi-port memory having a first port and a second port, the method comprising:
 segmenting a first portion of the memory corresponding to the first port; 
 writing data, using the second port, to a memory location in the first portion of the memory; and 
 reading data on the first port. 
 
   
   
     2. The method of  claim 1  further comprising:
 segmenting a second portion of the memory corresponding to the second port. 
 
   
   
     3. The method of  claim 2  further comprising:
 writing data, using the second port, to a memory location in the second portion of the memory. 
 
   
   
     4. The method of  claim 3  further comprising:
 reading the data written to a memory location in the second portion of the memory on the first port. 
 
   
   
     5. A method for testing a multi-port memory having a first port and a second port, the method comprising:
 segmenting a first portion of the memory corresponding to the first port; 
 segmenting a second portion of the memory corresponding to the second port; 
 writing data, using the second port, to a first memory location in the first portion of the memory; 
 reading data on the first port from the first memory location; 
 writing data, using the second port, to a second memory location in the second portion of the memory; and 
 reading data on the first port from the second memory location. 
 
   
   
     6. A method for testing a multi-port memory comprising:
 segmenting a first portion of the memory corresponding to a first port; and 
 testing a second port by writing data to the first portion of the memory corresponding to the first port. 
 
   
   
     7. The method of  claim 6  further comprising:
 reading data on the first port. 
 
   
   
     8. The method of  claim 7  further comprising:
 segmenting a second portion of the memory corresponding to a second port; and 
 testing a second port by
 writing data to the to the second portion of the memory; and 
 reading data on the first port. 
 
 
   
   
     9. An integrated circuit having a multi-port memory comprising:
 means for segmenting a portion of the memory corresponding to a first port; and 
 means for testing a second port by writing data to the portion of the memory corresponding to the first port. 
 
   
   
     10. The integrated circuit of  claim 9  comprising:
 means for reading data on the first port. 
 
   
   
     11. The method of  claim 10  further comprising:
 means for segmenting a second portion of the memory corresponding to a second port; and 
 means for testing a second port by
 writing data to the to the second portion of the memory; and 
 reading data on the first port. 
 
 
   
   
     12. An integrated circuit having a multi-port memory comprising:
 means for segmenting a first portion of the memory corresponding to a first port; 
 means for segmenting a second portion of the memory corresponding to a second port; 
 means for writing data, using the second port, to a first memory location in the first portion of the memory; 
 means for reading data on the first port from the first memory location; 
 means for writing data, using the second port, to a second memory location in the second portion of the memory; and 
 means for reading data on the first port from the second memory location.