Inventor
GREGOR STEVEN L
US19 patents
⚠️ This page may combine multiple inventors who share the name “GREGOR STEVEN L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
11 patentsUS5023776AJun 11, 1991
Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage
IBM228 citations98
US5450563ASep 12, 1995
Storage protection keys in two level cache system
IBM59 citations96
US5553305ASep 3, 1996
System for synchronizing execution by a processing element of threads within a process using a state indicator
IBM93 citations95
US5276848AJan 4, 1994
Shared two level cache including apparatus for maintaining storage consistency
IBM184 citations94
US7003704B2Feb 21, 2006
Two-dimensional redundancy calculation
IBM20 citations92
US6874111B1Mar 29, 2005
System initialization of microcode-based memory built-in self-test
IBM48 citations92
US6651201B1Nov 18, 2003
Programmable memory built-in self-test combining microcode and finite state machine self-test
IBM36 citations92
US5313613AMay 17, 1994
Execution of storage-immediate and storage-storage instructions within cache buffer storage
IBM24 citations92
US5226169AJul 6, 1993
System for execution of storage-immediate and storage-storage instructions within cache buffer storage
IBM23 citations92
US4924466AMay 8, 1990
Direct hardware error identification method and apparatus for error recovery in pipelined processing areas of a computer system
IBM37 citations91
US6907554B2Jun 14, 2005
Built-in self test system and method for two-dimensional memory redundancy allocation
IBM11 citations72
CADENCE DESIGN SYSTEMS INC
6 patentsUS7168005B2Jan 23, 2007
Programable multi-port memory BIST with compact microcode
CADENCE DESIGN SYSTEMS INC91 citations97
US6557127B1Apr 29, 2003
Method and apparatus for testing multi-port memories
CADENCE DESIGN SYSTEMS INC67 citations95
US11971818B1Apr 30, 2024
Memory view for non-volatile memory module
CADENCE DESIGN SYSTEMS INC0 citations51
US11966633B1Apr 23, 2024
Control algorithm generator for non-volatile memory module
CADENCE DESIGN SYSTEMS INC0 citations51
US7032144B2Apr 18, 2006
Method and apparatus for testing multi-port memories
CADENCE DESIGN SYSTEMS INC1 citations51
US12417029B1Sep 16, 2025
Memory view for memory module
CADENCE DESIGN SYSTEMS INC0 citations47