Inventor

MATHEWS GREGORY S

US52 patents

⚠️ This page may combine multiple inventors who share the name “MATHEWS GREGORY S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MATHEWS GREGORY S

APPLE INC

Memory request management system

Memory arbitration techniques based on latency tolerance

Memory access quality-of-service reallocation

Memory error tracking and logging

Temperature-based bandwidth compensation for memory traffic

Write/read turn techniques based on latency tolerance

Memory access scheduling using category arbitration

System and method for performing per-bank memory refresh

Write arbiter circuit with per-rank allocation override mode

Memory device bandwidth optimization

Memory error tracking and logging

Memory device bandwidth optimization

Multi-activation techniques for partial write operations

Decoding status flag techniques for memory circuits

Memory bank hotspotting

Data corruption tracking for memory reliability

Ordering memory requests based on access efficiency

Systems and methods for dynamically switching memory performance states

Handling eviction write operations caused by rate-limited traffic

Read arbiter circuit with dual memory rank support

Communication channels with both shared and independent resources

Ordering memory requests based on access efficiency

Memory request management system

INTEL CORP

Microprocessor with digital power throttle

Method and apparatus for independently stopping and restarting functional units

Method and apparatus for independently stopping and restarting functional units

Apparatus and method for reducing power consumption due to cache and TLB accesses in a processor front-end

Method and apparatus for managing temporal and non-temporal data in a single cache structure

Dual-ported, pipelined, two level cache system

Method and apparatus to provide advanced load ordering

System and method for translation buffer accommodating multiple page sizes

Hierarchical fully-associative-translation lookaside buffer structure

Method and apparatus for managing a memory array

Method and apparatus for accessing a cache using index prediction

Central processing unit address pipelining

Method and apparatus for reduced latency in hold bus cycles

Processing ordered data requests to a memory

Multi-processing cache coherency protocol on a local bus

Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small write back second level that allocates for CPU write misses only

TLB using region ID prevalidation

High performance fully dual-ported, pipelined cache design

Method and apparatus for set associative cache tag error detection

Unaligned semaphore adder

Processing ordered data requests to a memory

ALCATEL LUCENT USA INC

Testing and error recovery across multiple switching fabrics

Pointer allocation by prime numbers

LUCENT TECHNOLOGIES INC

Using reassembly queue sets for packet reassembly

Optimal load balancing across multiple switching fabrics

ALCATEL LUCENT

Hierarchical rate limiting with proportional limiting

ACATEL LUCENT USA INC

Flow control in a distributed scalable, shared memory switching fabric system