Inventor · disambiguated record
Michael K. Harper
Also filed as: HARPER MICHAEL · HARPER MICHAEL K
18 granted patents·5 pending applications·60 citations·filing 2006–2024
91Inventor score
Top patents by PatentIndex Score
23 records- 0194US8441074B2Substrate fins with different heightsRACHMADY WILLY·Filed 2010·Granted May 14, 2013·21 cites·20 claims
- 0290US8193641B2Recessed workfunction metal in CMOS transistor gatesRACHMADY WILLY·Filed 2006·Granted Jun 5, 2012·21 cites·9 claims
- 0381US11569231B2Non-planar transistors with channel regions having varying widthsINTEL CORP·Filed 2019·Granted Jan 31, 2023·3 cites·21 claims
- 0480US8629039B2Substrate fins with different heightsRACHMADY WILLY·Filed 2013·Granted Jan 14, 2014·4 cites·12 claims
- 0580US8314034B2Feature size reductionTAN ELLIOT N·Filed 2010·Granted Nov 20, 2012·7 cites·20 claims
- 0677US12457771B2Plug and recess process for dual metal gate on stacked nanoribbon devicesINTEL CORP·Filed 2024·Granted Oct 28, 2025·0 cites·26 claims
- 0775US12369392B2Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gatesINTEL CORP·Filed 2024·Granted Jul 22, 2025·0 cites·20 claims
- 0872US11972979B21D vertical edge blocking (VEB) via and plugINTEL CORP·Filed 2023·Granted Apr 30, 2024·0 cites·22 claims
- 0967US2023163215A1Gate-all-around integrated circuit structures having fin stack isolationINTEL CORP·Filed 2023·Application pending·0 cites
- 1066US2024363628A1Fabrication of gate-all-around integrated circuit structures having adjacent island structuresINTEL CORP·Filed 2024·Application pending·0 cites
- 1164US12046652B2Plug and recess process for dual metal gate on stacked nanoribbon devicesINTEL CORP·Filed 2020·Granted Jul 23, 2024·0 cites·16 claims
- 1264US8377771B2Recessed workfunction metal in CMOS transistor gatesINTEL CORP·Filed 2012·Granted Feb 19, 2013·2 cites·24 claims
- 1364US7977248B2Double patterning with single hard maskINTEL CORP·Filed 2007·Granted Jul 12, 2011·2 cites·20 claims
- 1463US11594637B2Gate-all-around integrated circuit structures having fin stack isolationINTEL CORP·Filed 2020·Granted Feb 28, 2023·0 cites·13 claims
- 1561US11990472B2Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gatesINTEL CORP·Filed 2020·Granted May 21, 2024·0 cites·11 claims
- 1656US12068314B2Fabrication of gate-all-around integrated circuit structures having adjacent island structuresINTEL CORP·Filed 2020·Granted Aug 20, 2024·0 cites·28 claims
- 1755US11721580B21D vertical edge blocking (VEB) via and plugINTEL CORP·Filed 2019·Granted Aug 8, 2023·0 cites·11 claims
- 1851US9905693B2Trigate transistor structure with unrecessed field insulator and thinner electrodes over the field insulatorINTEL CORP·Filed 2017·Granted Feb 27, 2018·0 cites·18 claims
- 1951US2009321834A1Substrate fins with different heightsRACHMADY WILLY·Filed 2008·Application pending·0 cites
- 2048US9768249B2Trigate transistor structure with unrecessed field insulator and thinner electrodes over the field insulatorINTEL CORP·Filed 2013·Granted Sep 19, 2017·0 cites·18 claims
- 2145US2021202478A1Gate-all-around integrated circuit structures having low aspect ratio isolation structures and subfinsINTEL CORP·Filed 2019·Application pending·0 cites
- 2242US9916988B2Sacrificial material for stripping masking layersINTEL CORP·Filed 2013·Granted Mar 13, 2018·0 cites·20 claims
- 2341US2020403081A1Recessed gate oxide on the sidewall of gate trenchSUNG SEUNG HOON·Filed 2019·Application pending·0 cites
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