Substrate fins with different heights

Abstract

A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.

1 - 12 . (canceled) 
     
     
         13 . A semiconductor device, comprising:
 a substrate;   a first multi-gate transistor on a first portion of the substrate, the first multi-gate transistor comprising a first fin, the first fin having a first height above a first isolation region; and   a second multi-gate transistor on a second portion of the substrate, the second multi-gate transistor comprising a second fin, the second fin having a second height above a second isolation region, the second height being greater than the first height.   
     
     
         14 . The device of  claim 13 , wherein the first multi-gate transistor is an N-type transistor and the second multi-gate transistor is a P-type transistor. 
     
     
         15 . The device of  claim 14 , further comprising a memory cell, wherein both the first and second multi-gate transistors are transistors of the memory cell. 
     
     
         16 . The device of  claim 14 , further comprising a ring oscillator, wherein both the first and second multi-gate transistors are transistors of the ring oscillator. 
     
     
         17 . The device of  claim 14  wherein the second height is greater than the first height in an amount great enough that the drive current of the first transistor is within 10% of the drive current of the second transistor. 
     
     
         18 . The device of  claim 17  wherein first multi-gate transistor has a first area, the second multi-gate transistor has a second area, and the first area is within about 15% of the second area. 
     
     
         19 . The device of  claim 13  wherein the second height is at least 25% greater than the first height. 
     
     
         20 . The device of  claim 13 , further comprising a third multi-gate transistor on a third portion of the substrate, the third multi-gate transistor comprising a third fin, the third fin having a third height above a third isolation region, the third height being greater than the second height.