Inventor

JHAVERI RITESH

US14 patents

⚠️ This page may combine multiple inventors who share the name “JHAVERI RITESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

13 patents

US9923054B2Mar 20, 2018

Fin structure having hard mask etch stop layers underneath gate sidewall spacers

INTEL CORP8 citations81

US9406547B2Aug 2, 2016

Techniques for trench isolation using flowable dielectric materials

INTEL CORP9 citations81

US11610889B2Mar 21, 2023

Arsenic-doped epitaxial, source/drain regions for NMOS

INTEL CORP3 citations72

US10204794B2Feb 12, 2019

Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures

INTEL CORP3 citations71

US11101268B2Aug 24, 2021

Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures

INTEL CORP0 citations60

US11875999B2Jan 16, 2024

Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures

INTEL CORP0 citations60

US11417531B2Aug 16, 2022

Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures

INTEL CORP0 citations60

US10950453B2Mar 16, 2021

Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures

INTEL CORP0 citations60

US10643855B2May 5, 2020

Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures

INTEL CORP0 citations50

JHAVERI RITESH

1 patent

US9048260B2Jun 2, 2015

Method of forming a semiconductor device with tall fins and using hard mask etch stops

JHAVERI RITESH14 citations77

JHAVERI RITESH

INTEL CORP

Fin structure having hard mask etch stop layers underneath gate sidewall spacers

Techniques for trench isolation using flowable dielectric materials

Arsenic-doped epitaxial, source/drain regions for NMOS

Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures

Transistors employing non-selective deposition of source/drain material

Techniques for trench isolation using flowable dielectric materials

Techniques for increasing channel region tensile strain in n-MOS devices

Arsenic-doped epitaxial source/drain regions for NMOS

Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures

Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures

Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures

Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures

Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures

JHAVERI RITESH

Method of forming a semiconductor device with tall fins and using hard mask etch stops