Techniques for trench isolation using flowable dielectric materials

Abstract

Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids. After curing, the resultant dielectric layer can undergo wet chemical, thermal, and/or plasma treatment, for instance, to modify at least one of its dielectric properties, density, and/or etch rate.

What is claimed is: 
     
       1. A method of forming an integrated circuit, the method comprising:
 depositing a flowable dielectric over a semiconductive substrate having first and second semiconductive fins extending from an upper surface thereof and a trench formed between the first and second semiconductive fins, wherein the trench has a width less than or equal to about 30 nm; 
 curing the flowable dielectric to form a dielectric layer over the semiconductive substrate, wherein the dielectric layer resides, at least in part, within the trench; and 
 treating the dielectric layer to modify at least one of its dielectric properties, density, and etch rate, wherein treating the dielectric layer comprises applying a thermal treatment that utilizes a furnace-based, vertical directional solidification (VDS) process in which the dielectric layer is subjected to an environment of about 90% steam or greater for a first period of time at a first temperature in the range of about 180-240° C. and for a second period of time at a second temperature in the range of about 450-525° C. 
 
     
     
       2. The method of  claim 1 , wherein depositing the flowable dielectric over the semiconductive substrate comprises using a flowable chemical vapor deposition (FCVD) process. 
     
     
       3. The method of  claim 2 , wherein the FCVD process utilizes remote plasma-enhanced CVD (RPECVD). 
     
     
       4. The method of  claim 1 , wherein the flowable dielectric comprises at least one of a silazane (SiH 2 NH) n -based polymer and Trisilylamine (N(SiH 3 ) 3 ). 
     
     
       5. The method of  claim 1 , wherein curing the flowable dielectric comprises exposing it to at least one of ozone (O 3 ) and oxygen (O 2 ). 
     
     
       6. The method of  claim 1 , wherein curing the flowable dielectric is performed at a temperature in the range of about 120-180° C. 
     
     
       7. The method of  claim 1 , wherein curing the flowable dielectric is performed at a pressure in the range of about 500-800 mTorr. 
     
     
       8. The method of  claim 1 , wherein curing the flowable dielectric to form the dielectric layer converts the flowable dielectric to at least one of an oxide, a nitride, and a carbide. 
     
     
       9. The method of  claim 1 , wherein treating the dielectric layer further comprises applying a wet chemical treatment that utilizes at least one of ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ), hot de-ionized water (HDIW), and de-ionized water (DIW). 
     
     
       10. The method of  claim 1 , wherein treating the dielectric layer further comprises applying a thermal treatment that utilizes at least one of furnace annealing, rapid thermal annealing, flash annealing, ultraviolet (UV) light-based oxidation, and a combination of any one or more thereof. 
     
     
       11. The method of  claim 1 , wherein the flowable dielectric extends over an upper surface of at least one of the first and second semiconductive fins. 
     
     
       12. The method of  claim 1 , wherein treating the dielectric layer further comprises applying a plasma treatment that utilizes at least one of a high-density plasma annealing process and a low-density plasma annealing process. 
     
     
       13. The method of  claim 1  further comprising planarizing the dielectric layer. 
     
     
       14. The method of  claim 1  further comprising etching the dielectric layer to recess it to a point below an active portion of at least one of the first and second semiconductive fins.