Inventor · disambiguated record
Henry Chung
Also filed as: CHUNG HENRY · CHUNG HENRY W · CHUNG HENRY WEI-MING
45 granted patents·6 pending applications·1,674 citations·filing 1990–2007
99Inventor score
Files withMACRONIX INT CO LTD22NAT SEMICONDUCTOR CORP9ALLIED SIGNAL INC8CHARTERED SEMICONDUCTOR MFG3HONEYWELL INT INC2
Top patents by PatentIndex Score
51 records- 0198US6955961B1Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolutionMACRONIX INT CO LTD·Filed 2004·Granted Oct 18, 2005·250 cites·63 claims
- 0298US6867116B1Fabrication method of sub-resolution pitch for integrated circuitsMACRONIX INT CO LTD·Filed 2003·Granted Mar 15, 2005·250 cites·20 claims
- 0393US6287955B1Integrated circuits with multiple low dielectric-constant inter-metal dielectricsALLIED SIGNAL INC·Filed 2000·Granted Sep 11, 2001·77 cites·8 claims
- 0492US6750150B2Method for reducing dimensions between patterns on a photoresistMACRONIX INT CO LTD·Filed 2001·Granted Jun 15, 2004·58 cites·21 claims
- 0591US6504247B2Integrated having a self-aligned Cu diffusion barrierALLIED SIGNAL INC·Filed 2002·Granted Jan 7, 2003·57 cites·7 claims
- 0691US5656543AFabrication of integrated circuits with borderless viasNAT SEMICONDUCTOR CORP·Filed 1995·Granted Aug 12, 1997·130 cites·11 claims
- 0788US6395607B1Integrated circuit fabrication method for self-aligned copper diffusion barrierALLIED SIGNAL INC·Filed 1999·Granted May 28, 2002·89 cites·13 claims
- 0886US5666007AInterconnect structures for integrated circuitsNAT SEMICONDUCTOR CORP·Filed 1995·Granted Sep 9, 1997·62 cites·59 claims
- 0985US6774051B2Method for reducing pitchMACRONIX INT CO LTD·Filed 2002·Granted Aug 10, 2004·36 cites·24 claims
- 1085US5691572AInterconnect structures for integrated circuitsNAT SEMICONDUCTOR CORP·Filed 1996·Granted Nov 25, 1997·60 cites·11 claims
- 1181US6812131B1Use of sacrificial inorganic dielectrics for dual damascene processes utilizing organic intermetal dielectricsHONEYWELL INT INC·Filed 2000·Granted Nov 2, 2004·34 cites·27 claims
- 1279US5094981ATechnique for manufacturing interconnections for a semiconductor device by annealing layers of titanium and a barrier material above 550° C.NORTH AMERICAN PHILIPS CORP SI·Filed 1990·Granted Mar 10, 1992·59 cites·25 claims
- 1378US6887627B2Method of fabricating phase shift maskMACRONIX INT CO LTD·Filed 2002·Granted May 3, 2005·17 cites·18 claims
- 1478US6063702AGlobal planarization method for inter level dielectric layers using IDL blocksCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted May 16, 2000·56 cites·13 claims
- 1578US5798299AInterconnect structures for integrated circuitsNAT SEMICONDUCTOR CORP·Filed 1996·Granted Aug 25, 1998·40 cites·24 claims
- 1678US5571751AInterconnect structures for integrated circuitsNAT SEMICONDUCTOR CORP·Filed 1994·Granted Nov 5, 1996·41 cites·10 claims
- 1777US6472124B1Self-aligned metal-insulator-metal capacitor for integrated circuitsMACRONIX INT CO LTD·Filed 2000·Granted Oct 29, 2002·20 cites·17 claims
- 1877US5352622AStacked capacitor with a thin film ceramic oxide layerNAT SEMICONDUCTOR CORP·Filed 1993·Granted Oct 4, 1994·41 cites·16 claims
- 1976US6946400B2Patterning method for fabricating integrated circuitMACRONIX INT CO LTD·Filed 2003·Granted Sep 20, 2005·18 cites·15 claims
- 2069US6097095AAdvanced fabrication method of integrated circuits with borderless vias and low dielectric-constant inter-metal dielectricsALLIED SIGNAL INC·Filed 1999·Granted Aug 1, 2000·37 cites·12 claims
- 2167US7033948B2Method for reducing dimensions between patterns on a photoresistMACRONIX INT CO LTD·Filed 2003·Granted Apr 25, 2006·9 cites·6 claims
- 2267US5792707AGlobal planarization method for inter level dielectric layers of integrated circuitsCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Aug 11, 1998·33 cites·17 claims
- 2367US5759886AMethod for forming a layer of metal silicide over the gates of a surface-channel CMOS deviceNAT SEMICONDUCTOR CORP·Filed 1996·Granted Jun 2, 1998·26 cites·34 claims
- 2466US6559045B2Fabrication of integrated circuits with borderless viasALLIED SIGNAL INC·Filed 2002·Granted May 6, 2003·9 cites·24 claims
- 2566US5646070AMethod of forming conductive region on silicon semiconductor material, and silicon semiconductor device with such regionPHILIPS ELECTRONICS NA·Filed 1995·Granted Jul 8, 1997·26 cites·13 claims
- 2664US7105099B2Method of reducing pattern pitch in integrated circuitsMACRONIX INT CO LTD·Filed 2004·Granted Sep 12, 2006·9 cites·22 claims
- 2764US6383912B1Fabrication method of integrated circuits with multiple low dielectric-constant intermetal dielectricsHONEYWELL INT INC·Filed 2000·Granted May 7, 2002·13 cites·32 claims
- 2863US7541271B2MOS transistors having low-resistance salicide gates and a self-aligned contact between them and method of manufactureMACRONIX INT CO LTD·Filed 2007·Granted Jun 2, 2009·2 cites·21 claims
- 2959US7605414B2MOS transistors having low-resistance salicide gates and a self-aligned contact between themMACRONIX INT CO LTD·Filed 2005·Granted Oct 20, 2009·1 cites·15 claims
- 3059US5757077AIntegrated circuits with borderless viasNAT SEMICONDUCTOR CORP·Filed 1996·Granted May 26, 1998·24 cites·4 claims
- 3158US6403424B1Method for forming self-aligned mask read only memory by dual damascene trenchesMACRONIX INT CO LTD·Filed 2001·Granted Jun 11, 2002·9 cites·18 claims
- 3257US6809018B2Dual salicides for integrated circuitsMACRONIX INT CO LTD·Filed 2002·Granted Oct 26, 2004·7 cites·18 claims
- 3355US6642139B1Method for forming interconnection structure in an integration circuitMACRONIX INT CO LTD·Filed 2002·Granted Nov 4, 2003·6 cites·9 claims
- 3454US7361604B2Method for reducing dimensions between patterns on a hardmaskMACRONIX INT CO LTD·Filed 2003·Granted Apr 22, 2008·4 cites·28 claims
- 3554US6709923B2Method for manufacturing an array structure in integrated circuitsMACRONIX INT CO LTD·Filed 2002·Granted Mar 23, 2004·2 cites·19 claims
- 3652US6734064B2Method for fabricating read only memory including forming masking layers with openings and pre-coding the cell and peripheral regionsMACRONIX INT CO LTD·Filed 2003·Granted May 11, 2004·4 cites·8 claims
- 3750US6498399B2Low dielectric-constant dielectric for etchstop in dual damascene backend of integrated circuitsALLIED SIGNAL INC·Filed 1999·Granted Dec 24, 2002·17 cites·24 claims
- 3849US5858875AIntegrated circuits with borderless viasNAT SEMICONDUCTOR CORP·Filed 1996·Granted Jan 12, 1999·16 cites·11 claims
- 3947US6790743B1[Method to relax alignment accuracy requirement in fabrication for integrated circuit]MACRONIX INT CO LTD·Filed 2003·Granted Sep 14, 2004·1 cites·19 claims
- 4045US6770975B2Integrated circuits with multiple low dielectric-constant inter-metal dielectricsALLIED SIGNAL INC·Filed 1999·Granted Aug 3, 2004·10 cites·9 claims
- 4141US6998316B2Method for fabricating read only memory including a first and second exposures to a photoresist layerMACRONIX INT CO LTD·Filed 2004·Granted Feb 14, 2006·1 cites·4 claims
- 4240US2004207091A1Integrated circuits with multiple low dielectric-constant inter-metal dielectricsWANG SHI-QING·Filed 2004·Application pending·0 cites
- 4339US6037253AMethod for increasing interconnect packing density in integrated circuitsCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Mar 14, 2000·8 cites·18 claims
- 4438US7303995B2Method for reducing dimensions between patterns on a photoresistMACRONIX INT CO LTD·Filed 2003·Granted Dec 4, 2007·0 cites·13 claims
- 4538US2003205815A1Fabrication method of integrated circuits with borderless vias and low dielectric constant inter-metal dielectricsFiled 2003·Application pending·0 cites
- 4638US2003224254A1Method for reducing dimensions between patterns on a photomaskMACRONIX INT CO LTD·Filed 2003·Application pending·0 cites
- 4737US6452275B1Fabrication of integrated circuits with borderless viasALLIED SIGNAL INC·Filed 1999·Granted Sep 17, 2002·5 cites·44 claims
- 4837US2004018697A1Method and structure of interconnection with anti-reflection coatingFiled 2002·Application pending·0 cites
- 4936US2002151165A1Advanced interconnection for integrated circuitsFiled 2001·Application pending·0 cites
- 5035US6713354B1Coding method for mask ROMMACRONIX INT CO LTD·Filed 2003·Granted Mar 30, 2004·0 cites·21 claims
Showing the top 50 of 51 patent records by PatentIndex Score.
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