Inventor

PAUL BIPUL C

US68 patents

⚠️ This page may combine multiple inventors who share the name “PAUL BIPUL C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAUL BIPUL C

GLOBALFOUNDRIES INC

Structures and SRAM bit cells with a buried cross-couple interconnect

Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming

Integrated circuit structure incorporating multiple gate-all-around field effect transistors having different drive currents and method

Methods of forming gate contact structures and cross-coupled contact structures for transistor devices

Cross couple structure for vertical transistors

Metal layer routing level for vertical FET SRAM and logic cell scaling

Structures and SRAM bit cells integrating complementary field-effect transistors

Integrated circuit structure with complementary field effect transistor and buried metal interconnect and method

Method of forming complementary nano-sheet/wire transistor devices with same depth contacts

Circuits based on complementary field-effect transistors

Two port SRAM cell using complementary nano-sheet/wire transistor devices

Methods of forming gate contact structures and cross-coupled contact structures for transistor devices

Buried local interconnect in source/drain region

Metal layer routing level for vertical FET SRAM and logic cell scaling

Active area shapes reducing device size

Resistive nonvolatile memory cells with shared access transistors

Bitcells for a non-volatile memory device

Method of forming a buried interconnect and the resulting devices

Magneto-resistive memory structures with improved sensing, and associated sensing methods

Integrated circuits having memory cells with shared bit lines and shared source lines

Six-transistor (6T) SRAM cell structure

Active area shapes reducing device size

Cross-coupled contact structure on IC products and methods of making such contact structures

Wordline strapping for non-volatile memory elements

Hierarchical layout versus schematic (LVS) comparison with extraneous device elimination

Dual port SRAM bitcell structures with improved transistor arrangement

Non-volatile memory elements with multiple access transistors

Dynamic bipolar write-assist for non-volatile memory elements

Static random access memory cells with arranged vertical-transport field-effect transistors

Dual port vertical transistor memory cell

GLOBALFOUNDRIES US INC

Gate contact structures and cross-coupled contact structures for transistor devices

Structures and SRAM bit cells integrating complementary field-effect transistors

Circuit structure and memory circuit with resistive memory elements, and related methods

Asymmetric gate cut isolation for SRAM

Sensing scheme for STT-MRAM using low-barrier nanomagnets

Non-volatile transistor embedded static random access memory (SRAM) cell

Apparatus and method for controlled transmitting of read pulse and write pulse in memory

Transistor arrays with controllable gate voltage

Non-volatile static random access memory bit cells with ferroelectric field-effect transistors

Sensing scheme for STT-MRAM using low-barrier nanomagnets

Gate contact structures and cross-coupled contact structures for transistor devices

Low variability reference parameter generation for magnetic random access memory

Capacitor integrated with memory element of memory cell

Twisted wordline structures

Sense circuit and high-speed memory structure incorporating the sense circuit

PAUL BIPUL C

Router design for 3D network-on-chip

Edge and strap cell design for SRAM array

Multi-valued ROM using carbon-nanotube and nanowire FET

TOSHIBA AMERICA RES INC

Memory based computation systems and methods of using the same

Memory based computation systems and methods for high performance and/or fast operations