Integrated circuit structure with complementary field effect transistor and buried metal interconnect and method

Abstract

Disclosed are structures with a complementary field effect transistor (CFET) and a buried metal interconnect that electrically connects a source/drain region of a lower-level transistor of the CFET with another device. The structure can include a memory cell with first and second CFETs, where each CFET includes a pull-up transistor stacked on and having a common gate with a pull-down transistor and each pull-down transistor has a common source/drain region with a pass-gate transistor. The metal interconnect connects a lower-level source/drain region of the first CFET (i.e., the common source/drain region of first pass-gate and pull-up transistors) to the common gate of the second CFET (i.e., to the common gate of second pull-down and pull-up transistors). Formation methods include forming an interconnect placeholder during lower-level source/drain region formation. After upper-level source/drain regions and replacement metal gates are formed, the interconnect placeholder is exposed, removed and replaced with a metal interconnect.

What is claimed is: 
     
       1. An integrated circuit structure comprising:
 a complementary field effect transistor comprising:
 first-type source/drain regions for a lower-level transistor; 
 an isolation layer above the first-type source/drain regions, wherein the isolation layer has an essentially planar top surface; and 
 second-type source/drain regions for an upper-level transistor above and immediately adjacent to the planar top surface of the isolation layer; 
 
 a metal interconnect entirely below a level of the planar top surface of the isolation layer; and 
 an isolation region, 
 wherein the metal interconnect has a first segment above and immediately adjacent to the isolation region and a second segment above and immediately adjacent to the isolation region and further perpendicular to the first segment, 
 wherein the first segment is in contact with a sidewall of a selected first-type source/drain region of the first-type source/drain regions of the lower-level transistor, 
 wherein the metal interconnect comprises a metal wire and a conductive liner immediately adjacent to bottom, side and top surfaces of the metal wire, and 
 wherein the isolation layer extends laterally onto the first segment of the metal interconnect. 
 
     
     
       2. The integrated circuit structure of  claim 1 , further comprising an additional field effect transistor that is positioned laterally adjacent and parallel to the complementary field effect transistor,
 wherein the additional field effect transistor comprises a gate, and 
 wherein the second segment of the metal interconnect is in contact with a metal gate conductor layer at a sidewall of the gate. 
 
     
     
       3. The integrated circuit structure of  claim 2 ,
 wherein a top surface of the metal wire in the first segment is entirely covered by the conductive liner, and 
 wherein a top surface of the metal wire in the second segment is devoid of the conductive liner. 
 
     
     
       4. The integrated circuit structure of  claim 2 , wherein the isolation layer extends laterally over the first segment such that the isolation layer is immediately adjacent to the conductive liner and wherein the integrated circuit structure further comprises a dielectric fill material on the second segment above and immediately adjacent to the metal wire. 
     
     
       5. The integrated circuit structure of  claim 2 , wherein the first segment further comprises a silicide layer positioned laterally between the sidewall of the selected first-type source/drain region of the lower-level transistor and the metal wire of the first segment of the metal interconnect. 
     
     
       6. The integrated circuit structure of  claim 2 , wherein the selected first-type source/drain region of lower-level transistor and the first segment of the metal interconnect have essentially co-planar top surfaces. 
     
     
       7. The integrated circuit structure of  claim 2 , further comprising a static random access memory cell,
 wherein, within the static random access memory cell, the complementary field effect transistor comprises: a first pull-down transistor and a first pull-up transistor stacked above the first pull-down transistor; and the additional field effect transistor comprises a second complementary field effect transistor comprising: a second pull-down transistor and a second pull-up transistor stacked above the second pull-down transistor, 
 wherein the static random access memory cell further comprises a first pass-gate transistor that abuts the first pull-down transistor and a second pass-gate transistor that abuts the second pull-down transistor, and 
 wherein the selected first-type source/drain region and the gate electrically connected by the metal interconnect are a common N-type source/drain region of the first pass-gate transistor and the first pull-down transistor and a common gate of the second pull-up transistor and the second pull-down transistor, respectively. 
 
     
     
       8. The integrated circuit structure of  claim 7 ,
 wherein a gate of the first pass-gate transistor is in end-to-end alignment with the common gate of the second pull-up transistor and the second pull-down transistor, 
 wherein a gate cut isolation region electrically isolates the gate of the first pass-gate transistor from the common gate of the second pull-up transistor and the second pull-down transistor, 
 wherein the first segment of the metal interconnect is parallel to the gate of the first pass-gate transistor and to the common gate of the second pull-up transistor and the second pull-down transistor, 
 wherein the first segment of the metal interconnect is further in contact with the gate cut isolation region, and 
 wherein the second segment of the metal interconnect is positioned laterally between the gate cut isolation region and an end of the common gate of the second pull-up transistor and the second pull-down transistor. 
 
     
     
       9. An integrated circuit structure comprising:
 a complementary field effect transistor comprising:
 first-type source/drain regions for a lower-level transistor; 
 an isolation layer above the first-type source/drain regions; and 
 second-type source/drain regions for an upper-level transistor on the isolation layer; 
 
 a metal interconnect in contact with a sidewall of a selected first-type source/drain region of the first-type source/drain regions of the lower-level transistor,
 wherein the metal interconnect comprises a metal wire and a conductive liner immediately adjacent to bottom, side and top surfaces of the metal wire, and 
 wherein the isolation layer extends laterally onto the metal interconnect; and 
 
 an additional field effect transistor that is positioned laterally adjacent and parallel to the complementary field effect transistor,
 wherein the additional field effect transistor comprises a gate, 
 wherein a first segment of the metal interconnect is in contact with the selected first-type source/drain region of the lower-level transistor, 
 wherein a second segment of the metal interconnect is perpendicular to the first segment and in contact with a metal gate conductor layer of the gate, 
 wherein a top surface of the metal wire in the first segment is entirely covered by the conductive liner, and 
 wherein a top surface of the metal wire in the second segment is devoid of the conductive liner. 
 
 
     
     
       10. The integrated circuit structure of  claim 9 , wherein the isolation layer extends laterally over the first segment such that the isolation layer is immediately adjacent to the conductive liner and wherein the integrated circuit structure further comprises a dielectric fill material on the second segment above and immediately adjacent to the metal wire. 
     
     
       11. The integrated circuit structure of  claim 9 , wherein the first segment further comprises a silicide layer positioned laterally between the sidewall of the selected first-type source/drain region of the lower-level transistor and the metal wire of the first segment of the metal interconnect. 
     
     
       12. The integrated circuit structure of  claim 9 , wherein the selected first-type source/drain region of lower-level transistor and the first segment of the metal interconnect have essentially co-planar top surfaces. 
     
     
       13. The integrated circuit structure of  claim 9 , further comprising a static random access memory cell,
 wherein, within the static random access memory cell, the complementary field effect transistor comprises: a first pull-down transistor and a first pull-up transistor stacked above the first pull-down transistor; and the additional field effect transistor comprises a second complementary field effect transistor comprising: a second pull-down transistor and a second pull-up transistor stacked above the second pull-down transistor, 
 wherein the static random access memory cell further comprises a first pass-gate transistor that abuts the first pull-down transistor and a second pass-gate transistor that abuts the second pull-down transistor, and 
 wherein the selected first-type source/drain region and the gate electrically connected by the metal interconnect are a common N-type source/drain region of the first pass-gate transistor and the first pull-down transistor and a common gate of the second pull-up transistor and the second pull-down transistor, respectively. 
 
     
     
       14. The integrated circuit structure of  claim 13 ,
 wherein a gate of the first pass-gate transistor is in end-to-end alignment with the common gate of the second pull-up transistor and the second pull-down transistor, 
 wherein a gate cut isolation region electrically isolates the gate of the first pass-gate transistor from the common gate of the second pull-up transistor and the second pull-down transistor, 
 wherein the first segment of the metal interconnect is parallel to the gate of the first pass-gate transistor and to the common gate of the second pull-up transistor and the second pull-down transistor, 
 wherein the first segment of the metal interconnect is further in contact with the gate cut isolation region, and 
 wherein the second segment of the metal interconnect is positioned laterally between the gate cut isolation region and an end of the common gate of the second pull-up transistor and the second pull-down transistor. 
 
     
     
       15. An integrated circuit structure comprising:
 a complementary field effect transistor comprising:
 first-type source/drain regions for a lower-level transistor; 
 an isolation layer above the first-type source/drain regions; and 
 second-type source/drain regions for an upper-level transistor on the isolation layer; 
 
 a metal interconnect in contact with a sidewall of a selected first-type source/drain region of the first-type source/drain regions of the lower-level transistor,
 wherein the metal interconnect comprises a metal wire and a conductive liner immediately adjacent to bottom, side and top surfaces of the metal wire, and 
 wherein the isolation layer extends laterally onto the metal interconnect; 
 
 additional field effect transistor that is positioned laterally adjacent and parallel to the complementary field effect transistor,
 wherein the additional field effect transistor comprises a gate, 
 wherein a first segment of the metal interconnect is in contact with the selected first-type source/drain region of the lower-level transistor, and 
 wherein a second segment of the metal interconnect is perpendicular to the first segment and in contact with a metal gate conductor layer of the gate; and 
 
 a static random access memory cell,
 wherein, within the static random access memory cell, the complementary field effect transistor comprises: a first pull-down transistor and a first pull-up transistor stacked above the first pull-down transistor; and the additional field effect transistor comprises a second complementary field effect transistor comprising: a second pull-down transistor and a second pull-up transistor stacked above the second pull-down transistor, 
 wherein the static random access memory cell further comprises a first pass-gate transistor that abuts the first pull-down transistor and a second pass-gate transistor that abuts the second pull-down transistor, and 
 wherein the selected first-type source/drain region and the gate electrically connected by the metal interconnect are a common N-type source/drain region of the first pass-gate transistor and the first pull-down transistor and a common gate of the second pull-up transistor and the second pull-down transistor, respectively. 
 
 
     
     
       16. The integrated circuit structure of  claim 15 ,
 wherein a top surface of the metal wire in the first segment is entirely covered by the conductive liner, and 
 wherein a top surface of the metal wire in the second segment is devoid of the conductive liner. 
 
     
     
       17. The integrated circuit structure of  claim 15 , wherein the isolation layer extends laterally over the first segment such that the isolation layer is immediately adjacent to the conductive liner and wherein the integrated circuit structure further comprises a dielectric fill material on the second segment above and immediately adjacent to the metal wire. 
     
     
       18. The integrated circuit structure of  claim 15 , wherein the first segment further comprises a silicide layer positioned laterally between the sidewall of the selected first-type source/drain region of the lower-level transistor and the metal wire of the first segment of the metal interconnect. 
     
     
       19. The integrated circuit structure of  claim 15 , wherein the selected first-type source/drain region of lower-level transistor and the first segment of the metal interconnect have essentially co-planar top surfaces. 
     
     
       20. The integrated circuit structure of  claim 19 ,
 wherein a gate of the first pass-gate transistor is in end-to-end alignment with the common gate of the second pull-up transistor and the second pull-down transistor, 
 wherein a gate cut isolation region electrically isolates the gate of the first pass-gate transistor from the common gate of the second pull-up transistor and the second pull-down transistor, 
 wherein the first segment of the metal interconnect is parallel to the gate of the first pass-gate transistor and to the common gate of the second pull-up transistor and the second pull-down transistor, 
 wherein the first segment of the metal interconnect is further in contact with the gate cut isolation region, and 
 wherein the second segment of the metal interconnect is positioned laterally between the gate cut isolation region and an end of the common gate of the second pull-up transistor and the second pull-down transistor.