Inventor

YAMAGUCHI JAMES

US9 patents

⚠️ This page may combine multiple inventors who share the name “YAMAGUCHI JAMES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IRVINE SENSORS CORP

2 patents

US7335576B2Feb 26, 2008

Method for precision integrated circuit die singulation using differential etch rates

IRVINE SENSORS CORP61 citations96

US7239012B2Jul 3, 2007

Three-dimensional module comprised of layers containing IC chips with overlying interconnect layers

IRVINE SENSORS CORP5 citations69

BINDRUP RANDY

2 patents

US8637985B2Jan 28, 2014

Anti-tamper wrapper interconnect method and a device

BINDRUP RANDY2 citations57

US9431275B2Aug 30, 2016

Wire bond through-via structure and method

BINDRUP RANDY1 citations46

OZGUZ VOLKAN

1 patent

US7786562B2Aug 31, 2010

Stackable semiconductor chip layer comprising prefabricated trench interconnect vias

OZGUZ VOLKAN11 citations77

LUDWIG DAVID

1 patent

USRE43877EDec 25, 2012

Method for precision integrated circuit die singulation using differential etch rates

LUDWIG DAVID1 citations50

PFG IP LLC

1 patent

US9741680B1Aug 22, 2017

Wire bond through-via structure and method

PFG IP LLC0 citations47

YAMAGUCHI JAMES

1 patent

US8637140B2Jan 28, 2014

Method for defining an electrically conductive metal structure on a three-dimensional element and a device made from the method

YAMAGUCHI JAMES0 citations33

LIEU PETER

1 patent

US8609473B2Dec 17, 2013

Method for fabricating a neo-layer using stud bumped bare die

LIEU PETER0 citations32