Method for precision integrated circuit die singulation using differential etch rates

Abstract

A preprocessed semiconductor substrate such as a wafer is provided with a metal etch mask which defines singulation channels on the substrate surface. An isotropic etch process is used to define a singulation channel with a first depth extending into the semiconductor substrate material. A second anisotropic etch process is used to increase the depth of the singulation channel while providing substantially vertical singulation channel sidewalls. The singulation channel can be extended through the depth of the substrate or, in an alternative embodiment, a predetermined portion of the inactive surface of the substrate removed to expose the singulation channels. In this manner, semiconductor die can be precisely singulated from a wafer while maintaining vertical die sidewalls.

1. A method for singulating an integrated circuit die from a semiconductor substrate comprised of the steps of, the method comprising:
 providing a semiconductor substrate comprising including a first surface and a second surface, 
 saidwherein the first surface havingcomprises at least one preformed integrated circuit die formed thereon, 
 saidwherein the at least one preformed integrated circuit die further comprisingincludes a metal etch mask as part of a metal layer defined by a reticle during at least one of the same semiconductor processing steps as used to fabricate said the at least one preformed integrated circuit die in a set of semiconductor foundry processes, and  
 saidwherein the metal etch mask is disposed below a oxynitride passivation layer, to define a first surface area,;  
 defining a singulation channel with a predetermined first depth on said the first surface area using a first etching process,; and, 
 increasing said the first depth to a predetermined second depth using a second etching process. 
 
     
     
       2. The method of  claim 1 , further comprising the step of removing a predetermined portion of said the second surface, whereby said the singulation channel is exposed on said the second surface whereby said such that the at least one preformd integrated circuit die is singulated from said another preformed integrated circuit die or from a portion of the semiconductor substrate. 
     
     
       3. The method of  claim 1 , wherein said the first etching process is a reactive ion etching process. 
     
     
       4. The method of  claim 1 , wherein said the second etching process is a deep reactive ion etching process. 
     
     
       5. The method of  claim 1 , wherein said the first etching process is an isotropic etching process. 
     
     
       6. The method of  claim 1 , wherein said the second etching process is an anisotropic etching process. 
     
     
       7. The method of  claim 1 , wherein said the first etching process is an isotropic etching process and said the second etching process is an anisotropic etching process. 
     
     
       8. The method of  claim 1 , wherein said the first etching process is a reactive ion etching process and said the second etching process is a deep reactive ion etching process. 
     
     
       9. The method of  claim 1 , wherein said the first depth is between 6-12 6 and 12 microns and said the second depth is between 50 and 70 microns. 
     
     
       10. The method of  claim 1 , wherein said the metal etch mask is comprised of comprises aluminum. 
     
     
       11. The method of  claim 1 , wherein said the metal etch mask is provided on said the first surface during a series of semiconductor process steps. 
     
     
       12. The method of  claim 2 , wherein said the predetermined portion is removed by a lapping process. 
     
     
       13. The method of  claim 2 , wherein said the predetermined portion is removed by a CMP chemical-mechanical polishing process. 
     
     
       14. The method of  claim 6 , wherein said the anisotropic etching process is performed at a temperature of between about −100 −100° C. and about −130 −130° C. 
     
     
       15. A method for singulating an integrated circuit, the method comprising:
 forming a singulation channel to a first depth in a substrate using a metal etch mask to define the singulation channel, wherein the metal etch mask is part of a metal layer of an integrated circuit defined by a reticle during one of the same semiconductor processing steps as used to fabricate the integrated circuit in a set of semiconductor foundry processes, and wherein the metal etch mask is located below an oxynitride passivation layer; and   extending the singulation channel to a second depth.    
     
     
       16. The method of claim 15, wherein the integrated circuit is formed on the substrate, and wherein the singulation channel is located between the integrated circuit and another integrated circuit formed on the substrate.  
     
     
       17. The method of claim 15, further comprising removing a portion of the substrate to expose the singulation channel and singulate the integrated circuit from another integrated circuit or from a portion of the substrate.  
     
     
       18. The method of claim 17, wherein said removing a portion of the substrate comprises at least one of lapping or grinding the substrate.  
     
     
       19. The method of claim 17, wherein said removing a portion of the substrate comprises polishing the substrate using a chemical-mechanical polishing process.  
     
     
       20. The method of claim 17, wherein said extending the singulation channel to a second depth comprises extending the singulation channel entirely through the substrate.  
     
     
       21. The method of claim 15, wherein said forming a singulation channel is performed using a first etching process, and wherein said extending the singulation channel to a second depth is performed using a second etching process.  
     
     
       22. The method of claim 21, wherein the first etching process comprises a reactive ion etching process.  
     
     
       23. The method of claim 21, wherein the second etching process comprises a deep reactive ion etching process.  
     
     
       24. The method of claim 21, wherein the first etching process comprises an isotropic etching process.  
     
     
       25. The method of claim 21, wherein the second etching process comprises an anisotropic etching process.  
     
     
       26. The method of claim 15, wherein the first depth is between 6 and 12 microns and the second depth is between 50 and 70 microns.  
     
     
       27. The method of claim 15, wherein the metal etch mask comprises aluminum.  
     
     
       28. The method of claim 15, further comprising removing at least a portion of the metal etch mask after said forming a singulation channel.  
     
     
       29. The method of claim 15, further comprising applying a photoresist layer over at least a portion of the integrated circuit, at least a portion of the oxynitride passivation layer, or at least a portion of a substrate upon which the integrated circuit is formed.  
     
     
       30. The method of claim 15, further comprising exposing the metal etch mask by removing at least a portion of the oxynitride passivation layer.  
     
     
       31. A method for singulating a die, the method comprising:
 etching a singulation channel in a substrate between a first integrated circuit and a second integrated circuit using a first etching process, wherein the singulation channel is formed to a first depth using a metal etch mask that is located below an oxynitride passivation layer and that is part of a metal layer of the first integrated circuit that is defined by a reticle during fabrication of the first integrated circuit in a set of semiconductor foundry processes; and   extending the singulation channel to a second depth using a second etching process that is different from the first etching process.    
     
     
       32. The method of claim 31, further comprising extending the singulation channel entirely through the substrate such that the first integrated circuit is singulated from the second integrated circuit or from a portion of the substrate.  
     
     
       33. The method of claim 31, further comprising removing a portion of the substrate to expose the singulation channel such that the first integrated circuit is singulated from the second integrated circuit or from a portion of the substrate.  
     
     
       34. The method of claim 33, wherein said removing a portion of the substrate comprises at least one of lapping the substrate or polishing the substrate using a chemical-mechanical polishing process.  
     
     
       35. The method of claim 31, wherein the first etching process is a reactive ion etching process and the second etching process is a deep reactive ion etching process.  
     
     
       36. The method of claim 31, wherein the first etching process is an isotropic etching process and the second etching process is an anisotropic etching process.  
     
     
       37. The method of claim 31, wherein the second etching process comprises alternating multiple etching phases with multiple passivation layer creation phases such that each etching phase is followed by a deposition of a passivation layer.  
     
     
       38. The method of claim 31, wherein the second etching process is performed between about −100° C. and −130° C.  
     
     
       39. The method of claim 31, further comprising applying a photoresist layer over at least a portion of the first integrated circuit, at least a portion of the oxynitride passivation layer, or at least a portion of the substrate.  
     
     
       40. The method of claim 31, further comprising exposing the metal etch mask by removing at least a portion of the oxynitride passivation layer.  
     
     
       41. The method of claim 31, further comprising removing all of the metal etch mask prior to said extending the singulation channel to a second depth.  
     
     
       42. The method of claim 41, further comprising:
 applying a first photoresist layer over at least a portion of the first integrated circuit, at least a portion of the oxynitride passivation layer, or at least a portion of the substrate prior to said etching a singulation channel; and   applying a second photoresist layer over at least a portion of the first integrated circuit or at least a portion of the substrate after said removing all of the metal etch mask.