Inventor
LEE TEK PO RINUS
US14 patents
Patents
14 patentsUS10103238B1Oct 16, 2018
Nanosheet field-effect transistor with full dielectric isolation
GLOBALFOUNDRIES INC57 citations98
US9831317B1Nov 28, 2017
Buried contact structures for a vertical field-effect transistor
GLOBALFOUNDRIES INC18 citations92
US10263122B1Apr 16, 2019
Methods, apparatus, and manufacturing system for self-aligned patterning of contacts in a vertical field effect transistor
GLOBALFOUNDRIES INC14 citations86
US10242982B2Mar 26, 2019
Method for forming a protection device having an inner contact spacer and the resulting devices
GLOBALFOUNDRIES INC3 citations72
US9876077B1Jan 23, 2018
Methods of forming a protection layer on an isolation region of IC products comprising FinFET devices
GLOBALFOUNDRIES INC5 citations72
US9570552B1Feb 14, 2017
Forming symmetrical stress liners for strained CMOS vertical nanowire field-effect transistors
GLOBALFOUNDRIES INC3 citations72
US10872979B2Dec 22, 2020
Spacer structures for a transistor device
GLOBALFOUNDRIES INC1 citations62
US10629739B2Apr 21, 2020
Methods of forming spacers adjacent gate structures of a transistor device
GLOBALFOUNDRIES INC1 citations62
US10230000B2Mar 12, 2019
Vertical-transport transistors with self-aligned contacts
GLOBALFOUNDRIES INC1 citations62
US10170544B2Jan 1, 2019
Integrated circuit products that include FinFET devices and a protection layer formed on an isolation region
GLOBALFOUNDRIES INC1 citations62
US10886178B2Jan 5, 2021
Device with highly active acceptor doping and method of production thereof
GLOBALFOUNDRIES INC0 citations58
US10276683B2Apr 30, 2019
Common metal contact regions having different Schottky barrier heights and methods of manufacturing same
GLOBALFOUNDRIES INC0 citations52
US9812543B2Nov 7, 2017
Common metal contact regions having different Schottky barrier heights and methods of manufacturing same
GLOBALFOUNDRIES INC0 citations52
US10109714B2Oct 23, 2018
Buried contact structures for a vertical field-effect transistor
GLOBALFOUNDRIES INC0 citations51