Integrated circuit products that include FinFET devices and a protection layer formed on an isolation region

Abstract

An integrated circuit product includes a FinFET device, a device isolation region that is positioned around a perimeter of the FinFET device, and an isolation protection layer that is positioned above the device isolation region. The FinFET device includes at least one fin, a gate structure, and a sidewall spacer, the device isolation region includes a first insulating material, and the isolation protection layer includes a material that is different from the first insulating material. A first portion of the isolation protection layer is positioned under a portion of the gate structure and under a portion of the sidewall spacer, wherein a second portion of the isolation protection layer is not positioned under the gate structure and is not positioned under the sidewall spacer, the first portion of the isolation protection layer having a thickness that is greater than a thickness of the second portion.

What is claimed: 
     
       1. An integrated circuit product, comprising:
 a FinFET device comprising at least one fin, a gate structure, and a sidewall spacer; 
 a device isolation region comprising a first insulating material positioned around a perimeter of said FinFET device; and 
 an isolation protection layer positioned above said device isolation region, said isolation protection layer comprising a material that is different from said first insulating material, wherein a first portion of said isolation protection layer is positioned under a portion of said gate structure and under a portion of said sidewall spacer, and wherein a second portion of said isolation protection layer is not positioned under said gate structure and is not positioned under said sidewall spacer, said first portion of said isolation protection layer having a thickness that is greater than a thickness of said second portion. 
 
     
     
       2. The integrated circuit product of  claim 1 , wherein said first insulating material comprises silicon dioxide and said isolation protection layer comprises one of silicon nitride and silicon oxynitride. 
     
     
       3. The integrated circuit product of  claim 1 , further comprising a conformal layer of insulating material positioned between said device isolation region and said isolation protection layer. 
     
     
       4. The integrated circuit product of  claim 3 , wherein said conformal layer of insulating material comprises silicon dioxide. 
     
     
       5. The integrated circuit product of  claim 1 , further comprising a recessed layer of a second insulating material positioned under said gate structure and adjacent to said at least one fin. 
     
     
       6. The integrated circuit product of  claim 5 , wherein said first and second insulating materials comprise silicon dioxide. 
     
     
       7. The integrated circuit product of  claim 5 , wherein said first and second insulating materials comprise different insulating materials. 
     
     
       8. The integrated circuit product of  claim 1 , wherein, when viewed in a cross-section taken through said gate structure and said isolation protection layer in a direction corresponding to a gate width direction of said FinFET device, said isolation protection layer has a substantially stepped cross-sectional profile. 
     
     
       9. The integrated circuit product of  claim 1 , wherein, when viewed in a cross-section taken through said gate structure and said isolation protection layer in a direction corresponding to a gate length direction of said FinFET device, said isolation protection layer has a substantially stepped cross-sectional profile. 
     
     
       10. An integrated circuit product, comprising:
 a FinFET device comprising at least one fin, a gate structure positioned on said at least one fin, and a sidewall spacer positioned adjacent to said gate structure; 
 a device isolation region positioned around a perimeter of said FinFET device, said device isolation structure comprising a first insulating material; and 
 an isolation protection layer that is positioned above said device isolation region, said isolation protection layer comprising a material that is different from said first insulating material, wherein a first portion of said isolation protection layer is positioned under a portion of said gate structure and under a portion of said sidewall spacer, and wherein a second portion of said isolation protection layer is not positioned under said gate structure and is not positioned under said sidewall spacer, said isolation protection layer having a substantially stepped cross-sectional profile such that a thickness of said first portion of said isolation protection layer is greater than a thickness of said second portion. 
 
     
     
       11. The integrated circuit product of  claim 10 , wherein said first insulating material comprises silicon dioxide and said isolation protection layer comprises one of silicon nitride and silicon oxynitride. 
     
     
       12. The integrated circuit product of  claim 10 , further comprising a conformal layer of insulating material positioned between said device isolation region and said isolation protection layer. 
     
     
       13. The integrated circuit product of  claim 12 , wherein said conformal layer of insulating material comprises silicon dioxide. 
     
     
       14. The integrated circuit product of  claim 10 , further comprising a recessed layer of a second insulating material positioned under said gate structure and adjacent to said at least one fin. 
     
     
       15. The integrated circuit product of  claim 14 , wherein said first and second insulating materials comprise silicon dioxide. 
     
     
       16. The integrated circuit product of  claim 14 , wherein said first and second insulating materials comprise different insulating materials. 
     
     
       17. The integrated circuit product of  claim 10 , wherein said isolation protection layer has said substantially stepped cross-sectional profile when viewed in a cross-section taken through said gate structure and said isolation protection layer in a gate width direction of said FinFET device. 
     
     
       18. The integrated circuit product of  claim 17 , wherein said isolation protection layer has said substantially stepped cross-sectional profile when viewed in a cross-section taken through said gate structure and said isolation protection layer in a gate length direction of said FinFET device. 
     
     
       19. An integrated circuit product, comprising:
 a FinFET device comprising at least one fin, a gate structure positioned on said at least one fin, and a sidewall spacer positioned adjacent to said gate structure; 
 a recessed layer of a first insulating material positioned under said gate structure and adjacent to said at least one fin; 
 a device isolation region positioned around a perimeter of said FinFET device, said device isolation structure comprising a second insulating material; 
 an isolation protection layer that is positioned above said device isolation region, said isolation protection layer comprising a material that is different from said second insulating material, wherein a first portion of said isolation protection layer is positioned under a portion of said gate structure and under a portion of said sidewall spacer, and wherein a second portion of said isolation protection layer is not positioned under said gate structure and is not positioned under said sidewall spacer, said isolation protection layer having a substantially stepped cross-sectional profile when viewed in cross-sections that are taken through said gate structure and said isolation protection layer in both a gate width direction and a gate length direction of said FinFET device. 
 
     
     
       20. The integrated circuit product of  claim 19 , wherein a thickness of said first portion of said isolation protection layer is greater than a thickness of said second portion of said isolation protection layer.