Inventor
HERRING JAY R
US30 patents
⚠️ This page may combine multiple inventors who share the name “HERRING JAY R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
27 patentsUS7187688B2Mar 6, 2007
Priority arbitration mechanism
IBM82 citations96
US6826123B1Nov 30, 2004
Global recovery for time of day synchronization
IBM50 citations96
US7058866B2Jun 6, 2006
Method and system for an on-chip AC self-test controller
IBM43 citations95
US6606326B1Aug 12, 2003
Packet switch employing dynamic transfer of data packet from central shared queue path to cross-point switching matrix path
IBM48 citations92
US7668923B2Feb 23, 2010
Master-slave adapter
IBM32 citations90
US7408875B2Aug 5, 2008
System and program product for actively managing central queue buffer allocation
IBM18 citations90
US7145837B2Dec 5, 2006
Global recovery for time of day synchronization
IBM21 citations90
US6373262B1Apr 16, 2002
Method and apparatus for testing a signal line
IBM30 citations89
US8799702B2Aug 5, 2014
Cable redundancy and failover for multi-lane PCI express IO interconnections
IBM12 citations84
US8645747B2Feb 4, 2014
Cable redundancy and failover for multi-lane PCI express IO interconnections
IBM6 citations84
US6618815B1Sep 9, 2003
Accurate distributed system time of day
IBM15 citations84
US7272764B2Sep 18, 2007
Method, system, and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit
IBM13 citations83
US6381643B1Apr 30, 2002
Mechanism and procedure for detecting switch mis-cabling
IBM14 citations83
US7792098B2Sep 7, 2010
Method for actively managing central queue buffer allocation
IBM8 citations82
US7308505B2Dec 11, 2007
Method, system and program product for facilitating forwarding of data packets through a node of a data transfer network using multiple types of forwarding tables
IBM7 citations73
US7272761B2Sep 18, 2007
Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit
IBM6 citations73
US7409613B2Aug 5, 2008
Simultaneous AC logic self-test of multiple clock domains
IBM7 citations71
US7409614B2Aug 5, 2008
Method, system and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit
IBM4 citations62
US7146587B2Dec 5, 2006
Scalable logic self-test configuration for multiple chips
IBM2 citations62
US7925728B2Apr 12, 2011
Facilitating detection of hardware service actions
IBM4 citations61
US7430698B2Sep 30, 2008
Method and system for an on-chip AC self-test controller
IBM1 citations61
US7619993B2Nov 17, 2009
Efficient probabilistic duplicate packet detector in computer networks
IBM3 citations60
US7774496B2Aug 10, 2010
System and program product for facilitating forwarding of data packets through a node of a data transfer network using multiple types of forwarding tables
IBM0 citations52
US8031639B2Oct 4, 2011
Efficient probabilistic duplicate packet detector in computer networks
IBM0 citations51
US7596734B2Sep 29, 2009
On-Chip AC self-test controller
IBM0 citations51
US7412638B2Aug 12, 2008
Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit
IBM0 citations51
US7573810B2Aug 11, 2009
Avoiding deadlocks in performing failovers in communications environments
IBM1 citations45