Method and system for an on-chip AC self-test controller

Abstract

A method and system for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation are provided. The method includes applying a long data capture pulse to a first test register in response to the system clock, applying an at speed data launch pulse to the first test register in response to the system clock, inputting the data from the first register to a logic path in response to applying the at speed data launch pulse to the first test register, applying an at speed data capture pulse to a second test register in response to the system clock, inputting the logic path output to the second test register in response to applying the at speed data capture pulse to the second test register, and applying a long data launch pulse to the second test register in response to the system clock.

1. A method for performing AC self-test on an integrated circuit that includes a system clock for normal operation, the method comprising:
 generating a sequence of data pulses based on the system clock, the sequence including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse, wherein the at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock; and 
 applying the sequence of data pulses to one or more test registers, wherein the long data capture pulse followed by the at speed data launch pulse tests a data launch operation and the at speed data capture pulse followed by the long data launch pulse tests a data capture operation. 
 
   
   
     2. The method of  claim 1  further comprising:
 initializing said one or more test registers with test data. 
 
   
   
     3. The method of  claim 2  wherein said initializing occurs using a scan technique. 
   
   
     4. The method of  claim 1  wherein the generating is performed by a clock splitter. 
   
   
     5. The method of  claim 1  further comprising:
 receiving the long data capture pulse and the at speed data capture pulse from a capture pulse output terminal of a clock splitter; and 
 receiving the long data launch pulse and the at speed data launch pulse from a launch pulse output terminal of the clock splitter. 
 
   
   
     6. The method of  claim 5  wherein data outputs from said capture pulse output terminal and said launch pulse output terminal are complements of each other during said AC self-test. 
   
   
     7. The method of  claim 5  wherein data outputs from said capture pulse output terminal and said launch pulse output terminal are created in response to said system clock and to an AC self-test controller. 
   
   
     8. The method of  claim 1  wherein the one or more test registers include a first test register and a second test register, data from the first test register is input to a logic path in response to applying the at speed data launch pulse, and output data from the logic path is input to the second test register in response to applying the at speed data capture pulse. 
   
   
     9. The method of  claim 8  further comprising:
 comparing the data value in said second test register to an expected value. 
 
   
   
     10. The method of  claim 9  further comprising:
 detecting an error in response to said comparing.