Inventor

FAYNEH EYAL

IL55 patents

⚠️ This page may combine multiple inventors who share the name “FAYNEH EYAL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FAYNEH EYAL

INTEL CORP

Third-order self-biased phase-locked loop for low jitter applications

Fast digital to time converter linearity calibration to improve clock jitter performance

Yank detection circuit for self-biased phase locked loops

Startup/yank circuit for self-biased phase-locked loops

Clock distribution phase alignment technique

On-chip filter-regulator for a microprocessor phase locked loop supply

Delay stage with controllably variable capacitive load

Voltage regulator

High-accuracy continuous duty-cycle correction circuit

High-performance charge pump for self-biased phase-locked loop

Method and apparatus for de-skewing a clock using a first and second phase locked loop and a clock tree

Method and apparatus for selectively disabling clock distribution

Scalable interleaved digital-to-time converter circuit for clock generation

On-chip filter-regulator, such as one for a microprocessor phase locked loop (PLL) supply

Adaptive integrated PLL loop filter

In-package RF waveguides as high bandwidth chip-to-chip interconnects and methods for using the same

Efficient integrated switching voltage regulator comprising switches coupled to bridge drivers to provide regulated power supply to power domains

Digital phase-locked loop supply voltage control

Method and apparatus to utilize a digital-time-conversion (DTC) based clocking in computing systems

Method and apparatus to utilize a digital-time-conversion (DTC) based clocking in computing systems

In-package RF waveguides as high bandwidth chip-to-chip interconnects and methods for using the same

Startup/yank circuit for self-biased phase-locked loops

Tracking bin split technique

Time-domain device noise simulator

Efficient integrated switching voltage regulator

PROTEANTECS LTD

Die-to-die and chip-to-chip connectivity monitoring

Integrated circuit margin measurement and failure prediction device

Die-to-die connectivity monitoring

Die-to-die connectivity monitoring using a clocked receiver

Integrated circuit pad failure detection

Integrated circuit margin measurement and failure prediction device

Integrated circuit margin measurement for structural testing

Integrated circuit profiling and anomaly detection

Integrated circuit workload, temperature and/or subthreshold leakage sensor

Integrated circuit I/O integrity and degradation monitoring

Efficient integrated circuit simulation and testing

Loopback testing of integrated circuits

Memory device degradation monitoring

Integrated circuit I/O integrity and degradation monitoring

Integrated circuit I/O integrity and degradation monitoring

Integrated circuit margin measurement and failure prediction device

Integrated circuit profiling and anomaly detection

Efficient integrated circuit simulation and testing

Integrated circuit workload, temperature, and/or sub-threshold leakage sensor

Thermal sensor for integrated circuit

Integrated circuit degradation estimation and time-of-failure prediction using workload and margin sensing

Die-to-die connectivity monitoring

Adaptive frequency scaling based on clock cycle time measurement

IBTEL CORP

Method for clock generator lock-time reduction during speedstep transition

SIZIKOV GREGORY

Efficient integrated switching voltage regulator comprising switches coupled to bridge drivers to provide regulated power supply to power domains