Inventor

KAXIRAS STEFANOS

SE31 patents

⚠️ This page may combine multiple inventors who share the name “KAXIRAS STEFANOS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAXIRAS STEFANOS

AGERE SYSTEMS INC

Method and apparatus for identifying splittable packets in a multithreaded VLIW processor

Method and apparatus for splitting packets in multithreaded VLIW processor

Method and apparatus for allocating functional units in a multithreaded VLIW processor

Method and apparatus for releasing functional units in a multithreaded VLIW processor

Directory-based prediction methods and apparatus for shared-memory multiprocessor systems

Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decay

Method and apparatus for reducing leakage power in a cache memory by using a timer control signal that removes power to associated cache lines

Set-associative memory architecture for routing tables

ETA SCALE AB

System and method for dynamic enforcement of store atomicity

Systems and methods for non-speculative store coalescing and generating atomic write sets using address subsets

Multi-core computer systems with private/shared cache line indicators

System and method for event monitoring in cache coherence protocols without explicit invalidations

System and method for self-invalidation, self-downgrade cachecoherence protocols

System and method for non-speculative reordering of load accesses

System and method for self-invalidation, self-downgrade cachecoherence protocols

Systems and methods for invisible speculative execution

SAMSUNG ELECTRONICS CO LTD

Systems and methods for direct data access in multi-level cache memory hierarchies

System protecting caches from side-channel attacks

Systems and methods for reducing first level cache energy by eliminating cache address tags

Systems and methods for implementing a tag-less shared cache and a larger backing cache

WISCONSIN ALUMNI RES FOUND

Multiple processor, distributed memory computer with out-of-order processing

Multiple processor, distributed memory computer with out-of-order processing

Multiple processor, distributed memory computer with out-of-order processing

ADVANCED RISC MACH LTD

Decoupled access-execute processing

Apparatus and method for handling memory load requests

Decoupled access-execute processing and prefetching control

KAXIRAS STEFANOS

System and method for simplifying cache coherence using multiple write policies

System and method for event monitoring in cache coherence protocols without explicit invalidations

CRAY RESEARCH INC

Distributed vector architecture

Interleaving memory in distributed vector architecture multiprocessor system

ROS ALBERTO

Systems and methods for coherence in clustered cache hierarchies