Inventor

CHU SANFORD

SG48 patents

⚠️ This page may combine multiple inventors who share the name “CHU SANFORD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHU SANFORD

CHARTERED SEMICONDUCTOR MFG

MIM and metal resistor formation at CU beol using only one extra mask

Darc layer for MIM process integration

Method of forming a surface coating layer within an opening within a body by atomic layer deposition

Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process

Method to fill a trench and tunnel by using ALD seed layer and electroless plating

Metal sandwich structure for MIM capacitor onto dual damascene

Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semiconductor technology by backside trench and fill

Silicon-based inductor with varying metal-to-metal conductor spacing

Method to enhance inductor Q factor by forming air gaps below inductors

Low noise inductor using electrically floating high resistive and grounded low resistive patterned shield

Method for forming a MIM capacitor

LDMOS using a combination of enhanced dielectric stress layer and dummy gates

Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process

Method of reducing substrate coupling for chip inductors by creation of dielectric islands by selective EPI deposition

Method to form fuse using polymeric films

Method of forming an inductor with continuous metal deposition

Process to reduce substrate effects by forming channels under inductor devices and around analog blocks

Process to reduce substrate effects by forming channels under inductor devices and around analog blocks

Method of making direct contact on gate by using dielectric stop layer

Method and device for reducing capacitive and magnetic effects from a substrate by using a schottky diode under passive components

Method of integrating triple gate oxide thickness

Use of a selective hard mask for the integration of double diffused drain MOS devices in deep sub-micron fabrication technologies

Method for forming a MIM (metal-insulator-metal) capacitor

Method of blocking nitrogen from thick gate oxide during dual gate CMP

MOSFET device with low gate contact resistance

Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits

Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits

Semiconductor structure including high voltage device

GLOBALFOUNDRIES SG PTE LTD

Channel surface technique for fabrication of FinFET devices

EEPROM cell

Dielectric stack

EEPROM cell

EEPROM cell

EEPROM cell

TAN CHUNG FOONG

Channel surface technique for fabrication of FinFET devices

Asymmetrical transistor device and method of fabrication

Asymmetrical transistor device and method of fabrication

GLOBALFOUNDRIES INC

Integrated circuits with resistor structures formed from MIM capacitor material and methods for fabricating same

Integrated circuits including a MIMCAP device and methods of forming the same for long and controllable reliability lifetime

Semiconductor structure including capacitors having different capacitor dielectrics and method for the formation thereof

CHU SANFORD

High performance LDMOS device having enhanced dielectric strain layer

LDMOS using a combination of enhanced dielectric stress layer and dummy gates

High performance LDMOS device having enhanced dielectric strain layer

TAN SHYUE SENG

Diffusion barrier and method of formation thereof

KOO JEOUNG MO

Semiconductor structure including high voltage device

TOH ENG HUAT

P-channel flash with enhanced band-to-band tunneling hot electron injection

XIAO HAN

High voltage FINFET structure

JUNG SUNG MUN

Dielectric stack