Low noise inductor using electrically floating high resistive and grounded low resistive patterned shield

Abstract

A novel complimentary shielded inductor on a semiconductor is disclosed. A region of electrically floating high resistive material is deposited between the inductor and the semiconductor substrate. The high resistive shield is patterned with a number of gaps, such that a current induced in the shield by the inductor does not have a closed loop path. The high resistive floating shield compliments a grounded low resistive shield to achieve higher performance inductors. In this fashion, noise in the substrate is reduced. The novel complimentary shield does not significantly degrade the figures of merit of the inductor, such as, quality factor and resonance frequency. In one embodiment, the grounded shield is made of patterned N-well (or P-well) structures. In still another embodiment, the low resistive electrically grounded shield is made of patterned Silicide, which may be formed on portions of the substrate itself.

We claim:  
     
       1. A shield for reducing electromagnetic effects generated in a semiconductor, said shield comprising: 
       a) an electrically floating high resistive material in said semiconductor, said high resistive material patterned to prevent current induced in said high resistive material from having a closed loop path, said pattern having a plurality of gaps; and  
       b) a grounded low resistive material in said semiconductor, said low resistive material being substantially adjacent said gaps.  
     
     
       2. The shield of  claim 1  wherein said high resistive material is an electrical insulator. 
     
     
       3. The shield of  claim 1  wherein said high resistive material comprises high sheet resistance silicon. 
     
     
       4. The shield of  claim 1  wherein said high resistive material has a resistance of greater than 10,000 Ohms. 
     
     
       5. The shield of  claim 1  wherein said semiconductor comprises: 
       a substrate;  
       an inter-metal dielectric disposed between said substrate and said high resistive material; and  
       said substrate comprises projections into said inter-metal dielectric upon which said low resistive material is formed, wherein said low resistive material is operable to substantially prevent an electromagnetic field from passing through to said substrate.  
     
     
       6. The shield of  claim 5  where said low resistive material comprises polysilicon. 
     
     
       7. The shield of  claim 1  wherein said low resistive material comprises a well structure. 
     
     
       8. The shield of  claim 7  wherein said low resistive material comprises an N-well structure. 
     
     
       9. The shield of  claim 7  wherein said low resistive material comprises a P-well structure. 
     
     
       10. The shield of  claim 1  wherein said high resistive material is non-metallic. 
     
     
       11. The shield of  claim 1  wherein said semiconductor comprises an element that is operable to generate electromagnetic energy, wherein said shield is operable to substantially reduce electromagnetic effects from said element in a substrate of said semiconductor. 
     
     
       12. The shield of  claim 1  wherein said semiconductor comprises an inductor. 
     
     
       13. A shielded silicon based inductor, comprising: 
       an inductor formed in a semiconductor; and  
       an electrically floating high resistive material disposed between said inductor and a substrate, said high resistive material having a pattern that is non-continuous such that current induced in said high resistive material from said inductor faces an open loop path, wherein said high resistive material has gaps.  
     
     
       14. The shielded silicon based inductor of  claim 13 , further comprising: 
       an electrically grounded low resistive material between said inductor and said substrate, said low resistive material being substantially adjacent said gaps.  
     
     
       15. The shielded silicon based inductor of  claim 14  wherein the ratio of resistivity between said high resistive material and said low resistive material is at least 1000. 
     
     
       16. The shielded silicon based inductor of  claim 13  wherein said high resistive material comprises lightly doped unsilicided polysilicon. 
     
     
       17. The inductor of  claim 14  wherein said semiconductor comprises: 
       an inter-metal dielectric disposed between said substrate and said high resistive material; and  
       said substrate comprises projections into said inter-metal dielectric upon which said low resistive material is formed, wherein said low resistive material is operable to substantially prevent an electromagnetic field from passing through to said substrate.  
     
     
       18. The inductor of  claim 17  where said low resistive material comprises highly doped silicided polysilicon. 
     
     
       19. The inductor of  claim 14  wherein said low resistive material comprises a well structure. 
     
     
       20. The inductor of  claim 19  wherein said low resistive material comprises an N-well structure. 
     
     
       21. The inductor of  claim 13  wherein said inductor comprises a spiral shape. 
     
     
       22. The inductor of  claim 13  wherein said inductor comprises a spiral of substantially concentric rectangles. 
     
     
       23. The inductor of  claim 13  wherein said inductor comprises a stacked formation. 
     
     
       24. The inductor of  claim 13  wherein said inductor comprises copper. 
     
     
       25. The inductor of  claim 13  wherein said inductor comprises aluminum. 
     
     
       26. The inductor of  claim 13  wherein said high resistive material is substantially non-conducting. 
     
     
       27. A shielded silicon based inductor, comprising: 
       an inductor formed in a semiconductor;  
       an electrically floating high resistive material disposed between said inductor and a substrate; and  
       an electrically grounded low resistive material between said inductor and said substrate.  
     
     
       28. The shielded silicon based inductor of  claim 27  wherein further comprising: 
       a substrate;  
       an inter-metal dielectric disposed between said substrate and said high resistive material; and  
       said substrate comprises projections into said inter-metal dielectric upon which said low resistive material is found.  
     
     
       29. The shielded silicon based inductor of  claim 28  where said low resistive material comprises silicided polysilicon. 
     
     
       30. The shielded silicon based inductor of  claim 27  wherein said low resistive material comprises a well structure. 
     
     
       31. The shielded silicon based inductor of  claim 27  wherein said inductor is polygonal shaped.