Inventor

CHAN LAP

US150 patents

⚠️ This page may combine multiple inventors who share the name “CHAN LAP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAN LAP

CHARTERED SEMICONDUCTOR MFG

Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer

Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials

Method of forming contact to polysilicon gate for MOS devices

Ti/titanium nitride and ti/tungsten nitride thin film resistors for thermal ink jet technology

Method of manufacturing copper interconnect with top barrier layer

Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance

Application of titanium nitride and tungsten nitride thin film resistor for thermal ink jet technology

Method to form a self-aligned CMOS inverter using vertical device integration

Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon

Method to form, and structure of, a dual damascene interconnect device

Method for planarized interconnect vias using electroless plating and CMP

Method to form a self-aligned CMOS inverter using vertical device integration

Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant

Method for forming a transistor gate dielectric with high-K and low-K regions

Method to form a low parasitic capacitance pseudo-SOI CMOS device

Damascene process for forming coplanar top surface of copper connector isolated by barrier layers in an insulating layer

Laser curing of spin-on dielectric thin films

Method for fabricating a MOS device

Creation of a self-aligned, ion implanted channel region, after source and drain formation

Method for shallow trench isolation

Embedded polysilicon gate MOSFET

Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology

Method to encapsulate copper plug for interconnect metallization

Method for making improved shallow trench isolation for semiconductor integrated circuits

Antifuse structure and method for manufacturing it

Method of making back gate contact for silicon on insulator technology

Passivation of copper interconnect surfaces with a passivating metal layer

Method of forming a surface coating layer within an opening within a body by atomic layer deposition

Method for forming variable-K gate dielectric

Nanocrystal flash memory device and manufacturing method therefor

Method to form and/or isolate vertical transistors

Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner

Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)

Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation

Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge

Method to form smaller channel with CMOS device by isotropic etching of the gate materials

Low voltage controllable transient trigger network for ESD protection

Copper interconnect with top barrier layer

ESD protection device for STI deep submicron technology

Method of planarization of an intermetal dielectric layer using chemical mechanical polishing

Barrier layer

Method to fill a trench and tunnel by using ALD seed layer and electroless plating

Method to form a cross network of air gaps within IMD layer

Method to encapsulate copper plug for interconnect metallization

Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semiconductor technology by backside trench and fill

Flash device having a large planar area ono interpoly dielectric

Method to deposit a seeding layer for electroless copper plating

UNIV SINGAPORE

Method for fabricating semiconductor devices with reduced junction diffusion

CHARTERED SEMICONDUCTOR MANU L

Passivation of copper interconnect surfaces with a passivating metal layer

CHARTERED SEMIDCONDUCTOR MANUF

Method of making a dual damascene antifuse structure