Method for shallow trench isolation

Abstract

A new method for forming planarized high quality oxide shallow trench isolation is described. A nitride layer overlying a pad oxide layer is provided over the surface of a semiconductor substrate. A plurality of isolation trenches is etched through the nitride and pad oxide layers into the semiconductor substrate wherein there is at least one first wide nitride region between two of the isolation trenches and at least one second narrow nitride region between another two of the isolation trenches. A high density plasma (HDP) oxide layer is deposited over the nitride layer filling the isolation trenches wherein the HDP oxide deposits more thickly in the first region over the wide nitride layer and deposits more thinly in the second region over the narrow nitride layer and wherein the difference in step heights of the HDP oxide between the first region and a region overlying an isolation trench is a first height. A layer of spin-on-glass is coated over the HDP oxide layer wherein the difference in step heights of the spin-on-glass material between the first region and the region overlying an isolation trench is a second height smaller than the first height. The spin-on-glass layer and portions of the HDP oxide layer in the first region are etched away. The spin-on-glass layer and HDP oxide layer remaining are polished away wherein the substrate is planarized.

What is claimed is: 
     
       1. A method of manufacturing an integrated circuit device comprising: providing a pad oxide layer over the surface of a semiconductor substrate;   depositing a nitride layer overlying said pad oxide layer;   etching a plurality of isolation trenches through said nitride and said pad oxide layers into said semiconductor substrate wherein there is at least one first wide nitride region between two of said isolation trenches and at least one second narrow nitride region between another two of said isolation trenches;   depositing a high density plasma oxide layer over said nitride layer and within said isolation trenches wherein said high density plasma oxide layer fills said isolation trenches and wherein said high density plasma oxide deposits more thickly in said first region over said wide nitride layer and deposits more thinly in said second region over said narrow nitride layer and wherein the difference in step heights of said high density plasma oxide between said first region and a third region overlying an isolation trench is a first height;   coating a layer of spin-on-glass over said high density plasma oxide layer wherein the difference in step heights of said spin-on-glass material between said first region and said third region is a second height smaller than said first height;   etching back said spin-on-glass layer and said portions of said high density plasma oxide layer in said first region;   polishing away said spin-on-glass layer and said high density plasma oxide layer remaining wherein said substrate is planarized; and   completing the fabrication of said integrated circuit device.   
     
     
       2. The method according to claim 1 wherein said silicon nitride layer has a thickness of between about 500 and 2000 Angstroms. 
     
     
       3. The method according to claim 1 wherein said high density plasma oxide layer is deposited to a thickness of between about 6000 and 10,000 Angstroms. 
     
     
       4. The method according to claim 1 wherein said first height is between about 4000 and 8000 Angstroms. 
     
     
       5. The method according to claim 1 wherein said spin-on-glass layer is coated to a thickness of between about 4000 and 8000 Angstroms. 
     
     
       6. The method according to claim 1 wherein said second height is between about 1000 and 3000 Angstroms. 
     
     
       7. The method according to claim 1 wherein said etching back is performed with an etch selectivity of spin-on-glass to high density plasma oxide of 1:1. 
     
     
       8. The method according to claim 1 wherein said polishing is done by chemical mechanical polishing. 
     
     
       9. The method according to claim 1 wherein said completing fabrication of said integrated circuit device comprises: etching away said silicon nitride layer;   removing said pad oxide layer whereby said trench isolation areas extend above the surface of said semiconductor substrate wherein said trench isolation areas above said surface of said semiconductor substrate have sharp corners;   depositing a sacrificial oxide layer overlying said isolation trenches and said semiconductor substrate;   etching away said sacrificial oxide layer whereby said sharp corners of said trench isolation areas are etched away and wherein said trench isolation areas above said surface of said semiconductor substrate now have rounded corners; and   fabricating semiconductor device structures in and on said semiconductor substrate between said isolation trenches.   
     
     
       10. The method according to claim 9 wherein said semiconductor device structures include gate electrodes and source and drain regions and electrical connections between said gate electrodes and said source and drain regions. 
     
     
       11. A method of manufacturing an integrated circuit device comprising: providing a pad oxide layer over the surface of a semiconductor substrate;   depositing a nitride layer overlying said pad oxide layer;   etching a plurality of isolation trenches through said nitride and said pad oxide layers into said semiconductor substrate wherein there is at least one first wide nitride region between two of said isolation trenches and at least one second narrow nitride region between another two of said isolation trenches;   depositing a high density plasma oxide layer over said nitride layer and within said isolation trenches wherein said high density plasma oxide layer fills said isolation trenches and wherein said high density plasma oxide deposits more thickly in said first region over said wide nitride layer and deposits more thinly in said second region over said narrow nitride layer and wherein the difference in step heights of said high density plasma oxide between said first region and a third region overlying an isolation trench is a first height;   coating a layer of spin-on-glass over said high density plasma oxide layer wherein the difference in step heights of said spin-on-glass material between said first region and said third region is a second height smaller than said first height;   etching back said spin-on-glass layer and said portions of said high density plasma oxide layer in said first region;   polishing away said spin-on-glass layer and said high density plasma oxide layer remaining wherein said substrate is planarized;   etching away said silicon nitride layer;   removing said pad oxide layer whereby said trench isolation areas extend above the surface of said semiconductor substrate wherein said trench isolation areas above said surface of said semiconductor substrate have sharp corners;   depositing a sacrificial oxide layer overlying said isolation trenches and said semiconductor substrate;   etching away said sacrificial oxide layer whereby said sharp corners of said trench isolation areas are etched away and wherein said trench isolation areas above said surface of said semiconductor substrate now have rounded corners; and   fabricating semiconductor device structures in and on said semiconductor substrate between said isolation trenches.   
     
     
       12. The method according to claim 11 wherein said silicon nitride layer has a thickness of between about 500 and 2000 Angstroms. 
     
     
       13. The method according to claim 11 wherein said high density plasma oxide layer is deposited to a thickness of between about 6000 and 10,000 Angstroms. 
     
     
       14. The method according to claim 11 wherein said first height is between about 4000 and 8000 Angstroms. 
     
     
       15. The method according to claim 11 wherein said spin-on-glass layer is coated to a thickness of between about 4000 and 8000 Angstroms. 
     
     
       16. The method according to claim 11 wherein said second height is between about 1000 and 3000 Angstroms. 
     
     
       17. The method according to claim 11 wherein said etching back is performed with an etch selectivity of spin-on-glass to high density plasma oxide of 1:1. 
     
     
       18. The method according to claim 11 wherein said polishing is done by chemical mechanical polishing. 
     
     
       19. The method according to claim 11 wherein said semiconductor device structures include gate electrodes and source and drain regions and electrical connections between said gate electrodes and said source and drain regions. 
     
     
       20. A method of forming shallow trench isolation in the fabrication of an integrated circuit device comprising: providing a pad oxide layer over the surface of a semiconductor substrate;   depositing a nitride layer overlying said pad oxide layer;   etching a plurality of isolation trenches through said nitride and said pad oxide layers into said semiconductor substrate wherein there is at least one first wide nitride region between two of said isolation trenches and at least one second narrow nitride region between another two of said isolation trenches;   depositing a high density plasma oxide layer over said nitride layer and within said isolation trenches wherein said high density plasma oxide layer fills said isolation trenches and wherein said high density plasma oxide deposits more thickly in said first region over said wide nitride layer and deposits more thinly in said second region over said narrow nitride layer and wherein the difference in step heights of said high density plasma oxide between said first region and a third region overlying an isolation trench is a first height;   coating a layer of spin-on-glass over said high density plasma oxide layer wherein the difference in step heights of said spin-on-glass material between said first region and said third region is a second height smaller than said first height; and   etching back said spin-on-glass layer and said portions of said high density plasma oxide layer in said first region completing the formation of said shallow trench isolation in the fabrication of said integrated circuit device.   
     
     
       21. The method according to claim 20 further comprising: polishing away said spin-on-glass layer and said high density plasma oxide layer remaining wherein said substrate is planarized;   etching away said silicon nitride layer;   removing said pad oxide layer whereby said trench isolation areas extend above the surface of said semiconductor substrate wherein said trench isolation areas above said surface of said semiconductor substrate have sharp corners;   depositing a sacrificial oxide layer overlying said isolation trenches and said semiconductor substrate; and   etching away said sacrificial oxide layer whereby said sharp corners of said trench isolation areas are etched away and wherein said trench isolation areas above said surface of said semiconductor substrate now have rounded corners.