Inventor · disambiguated record
Lap Chan
Also filed as: CHAN LAP · CHAN LAP CHI
21 granted patents·1,164 citations·filing 1995–2021
97Inventor score
Files withCHARTERED SEMICONDUCTOR MFG18CHAN LAP CHI1CHARTERED SEMICONDUCTOR MFG CO1CHARTERED SEMIDCONDUCTOR MANUF1
Top patents by PatentIndex Score
21 records- 0197US5710070AApplication of titanium nitride and tungsten nitride thin film resistor for thermal ink jet technologyCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Jan 20, 1998·146 cites·20 claims
- 0296US5731239AMethod of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistanceCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Mar 24, 1998·174 cites·19 claims
- 0394US5744376AMethod of manufacturing copper interconnect with top barrier layerCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Apr 28, 1998·135 cites·13 claims
- 0492US5728621AMethod for shallow trench isolationCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Mar 17, 1998·171 cites·21 claims
- 0588US11448373B1Photosensitive candleCHAN LAP CHI·Filed 2021·Granted Sep 20, 2022·3 cites·20 claims
- 0687US5610083AMethod of making back gate contact for silicon on insulator technologyCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Mar 11, 1997·98 cites·28 claims
- 0784US5602053AMethod of making a dual damascene antifuse structureCHARTERED SEMIDCONDUCTOR MANUF·Filed 1996·Granted Feb 11, 1997·89 cites·8 claims
- 0879US5705849AAntifuse structure and method for manufacturing itCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Jan 6, 1998·55 cites·13 claims
- 0978US5627094AStacked container capacitor using chemical mechanical polishingCHARTERED SEMICONDUCTOR MFG·Filed 1995·Granted May 6, 1997·40 cites·21 claims
- 1077US6777774B2Low noise inductor using electrically floating high resistive and grounded low resistive patterned shieldCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Aug 17, 2004·29 cites·31 claims
- 1176US5808855AStacked container capacitor using chemical mechanical polishingCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Sep 15, 1998·35 cites·6 claims
- 1275US5618384AMethod for forming residue free patterned conductor layers upon high step height integrated circuit substrates using reflow of photoresistCHARTERED SEMICONDUCTOR MFG·Filed 1995·Granted Apr 8, 1997·61 cites·18 claims
- 1363US6188135B1Copper interconnect with top barrier layerCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Feb 13, 2001·22 cites·31 claims
- 1462US5900672ABarrier layerCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted May 4, 1999·21 cites·5 claims
- 1560US5677238ASemiconductor contact metallizationCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Oct 14, 1997·27 cites·12 claims
- 1652US5652152AProcess having high tolerance to buried contact mask misalignment by using a PSG spacerCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Jul 29, 1997·16 cites·23 claims
- 1745US5792708AMethod for forming residue free patterned polysilicon layers upon high step height integrated circuit substratesCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Aug 11, 1998·13 cites·23 claims
- 1843US5742088AProcess having high tolerance to buried contact mask misalignment by using a PSG spacerCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Apr 21, 1998·9 cites·3 claims
- 1940US5624871AMethod for making electrical local interconnectsCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Apr 29, 1997·12 cites·19 claims
- 2036US6307248B1Definition of anti-fuse cell for programmable gate array applicationCHARTERED SEMICONDUCTOR MFG CO·Filed 1999·Granted Oct 23, 2001·4 cites·20 claims
- 2134US5693178AElectrical test structure to quantify microloading after plasma dry etching of metal filmCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Dec 2, 1997·4 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →