Inventor · disambiguated record
Jia Zhen Zheng
Also filed as: CHAN LAP · ZHENG JIA Z · ZHENG JIA ZHEN
87 granted patents·9 pending applications·2,697 citations·filing 1996–2006
99Inventor score
Files withCHARTERED SEMICONDUCTOR MFG92CHAN TZE HO SIMON1CHARTERED SEMICONDUCTOR MFG CO1CHARTERED SEMIONDUCTOR MFG LTD1YELEHANKA PRADEEP RAMACHANDRAMURTHY1
Top patents by PatentIndex Score
96 records- 0198US6743291B2Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growthCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jun 1, 2004·125 cites·28 claims
- 0297US6300177B1Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materialsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 9, 2001·175 cites·26 claims
- 0396US6461900B1Method to form a self-aligned CMOS inverter using vertical device integrationCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 8, 2002·141 cites·22 claims
- 0494US6747314B2Method to form a self-aligned CMOS inverter using vertical device integrationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jun 8, 2004·93 cites·11 claims
- 0594US6313008B1Method to form a balloon shaped STI using a micro machining technique to remove heavily doped siliconCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Nov 6, 2001·90 cites·30 claims
- 0694US5744376AMethod of manufacturing copper interconnect with top barrier layerCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Apr 28, 1998·135 cites·13 claims
- 0793US6664156B1Method for forming L-shaped spacers with precise width controlCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 16, 2003·76 cites·17 claims
- 0893US6632712B1Method of fabricating variable length vertical transistorsCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 14, 2003·89 cites·31 claims
- 0992US5728621AMethod for shallow trench isolationCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Mar 17, 1998·171 cites·21 claims
- 1091US6406945B1Method for forming a transistor gate dielectric with high-K and low-K regionsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 18, 2002·59 cites·17 claims
- 1191US6403485B1Method to form a low parasitic capacitance pseudo-SOI CMOS deviceCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 11, 2002·66 cites·27 claims
- 1290US7081378B2Horizontal TRAM and method for the fabrication thereofCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Jul 25, 2006·45 cites·15 claims
- 1390US6468851B1Method of fabricating CMOS device with dual gate electrodeCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 22, 2002·55 cites·39 claims
- 1489US6417056B1Method to form low-overlap-capacitance transistors by forming microtrench at the gate edgeCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jul 9, 2002·51 cites·27 claims
- 1589US6306715B1Method to form smaller channel with CMOS device by isotropic etching of the gate materialsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 23, 2001·46 cites·14 claims
- 1688US6716693B1Method of forming a surface coating layer within an opening within a body by atomic layer depositionCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Apr 6, 2004·49 cites·28 claims
- 1788US6670248B1Triple gate oxide process with high-k gate dielectricCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 30, 2003·48 cites·15 claims
- 1888US6511884B1Method to form and/or isolate vertical transistorsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jan 28, 2003·48 cites·27 claims
- 1988US6468877B1Method to form an air-gap under the edges of a gate electrode by using disposable spacer/linerCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 22, 2002·53 cites·21 claims
- 2087US6903013B2Method to fill a trench and tunnel by using ALD seed layer and electroless platingCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Jun 7, 2005·44 cites·54 claims
- 2187US6734082B2Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shapeCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted May 11, 2004·45 cites·28 claims
- 2287US6709912B1Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimizationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 23, 2004·53 cites·27 claims
- 2387US6436770B1Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantationCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Aug 20, 2002·45 cites·19 claims
- 2484US6762085B2Method of forming a high performance and low cost CMOS deviceCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jul 13, 2004·36 cites·27 claims
- 2583US6830971B2High K artificial lattices for capacitor applications to use in CU or AL BEOLCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 14, 2004·26 cites·40 claims
- 2683US6709934B2Method for forming variable-K gate dielectricCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 23, 2004·26 cites·10 claims
- 2782US6140237ADamascene process for forming coplanar top surface of copper connector isolated by barrier layers in an insulating layerCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Oct 31, 2000·68 cites·27 claims
- 2881US7015101B2Multi-level gate SONOS flash memory device with high voltage oxide and method for the fabrication thereofCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Mar 21, 2006·22 cites·9 claims
- 2980US6268251B1Method of forming MOS/CMOS devices with dual or triple gate oxideCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jul 31, 2001·27 cites·24 claims
- 3078US7285804B2Thyristor-based SRAMCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Oct 23, 2007·6 cites·10 claims
- 3178US6403425B1Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxideCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 11, 2002·25 cites·36 claims
- 3278US6235591B1Method to form gate oxides of different thicknesses on a silicon substrateCHARTERED SEMICONDUCTOR MFG CO·Filed 1999·Granted May 22, 2001·46 cites·20 claims
- 3376US7183590B2Horizontal tramCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Feb 27, 2007·5 cites·10 claims
- 3476US6455377B1Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)CHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Sep 24, 2002·21 cites·35 claims
- 3575US7501683B2Integrated circuit with protected implantation profiles and method for the formation thereofCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Mar 10, 2009·4 cites·10 claims
- 3674US6566208B2Method to form elevated source/drain using poly spacerCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted May 20, 2003·22 cites·19 claims
- 3773US7176094B2Ultra-thin gate oxide through post decoupled plasma nitridation annealCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Feb 13, 2007·15 cites·15 claims
- 3873US6664153B2Method to fabricate a single gate with dual work-functionsCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 16, 2003·18 cites·22 claims
- 3973US6429109B1Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gateCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Aug 6, 2002·18 cites·35 claims
- 4072US6841441B2Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealingCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Jan 11, 2005·12 cites·37 claims
- 4172US6461887B1Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growthCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 8, 2002·18 cites·21 claims
- 4272US6380088B1Method to form a recessed source drain on a trench side wall with a replacement gate techniqueCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Apr 30, 2002·19 cites·29 claims
- 4372US6207554B1Gap filling process in integrated circuits using low dielectric constant materialsCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Mar 27, 2001·39 cites·22 claims
- 4472US6124215AApparatus and method for planarization of spin-on materialsCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Sep 26, 2000·36 cites·22 claims
- 4571US7382027B2MOSFET device with low gate contact resistanceCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Jun 3, 2008·4 cites·23 claims
- 4671US6610575B1Forming dual gate oxide thickness on vertical transistors by ion implantationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Aug 26, 2003·16 cites·47 claims
- 4770US8304834B2Semiconductor local interconnect and contactYELEHANKA PRADEEP RAMACHANDRAMURTHY·Filed 2006·Granted Nov 6, 2012·6 cites·5 claims
- 4870US6069069AMethod for planarizing a low dielectric constant spin-on polymer using nitride etch stopCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted May 30, 2000·38 cites·26 claims
- 4969US6303449B1Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMPCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 16, 2001·12 cites·11 claims
- 5068US6605501B1Method of fabricating CMOS device with dual gate electrodeCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Aug 12, 2003·14 cites·36 claims
Showing the top 50 of 96 patent records by PatentIndex Score.
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