Inventor

KRONHOLZ STEPHAN

DE72 patents

⚠️ This page may combine multiple inventors who share the name “KRONHOLZ STEPHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KRONHOLZ STEPHAN

KRONHOLZ STEPHAN

Transistor with embedded Si/Ge material having reduced offset to the channel region

Transistor with embedded Si/Ge material having reduced offset and superior uniformity

Reducing silicide resistance in silicon/germanium-containing drain/source regions of transistors

Embedded sigma-shaped semiconductor alloys formed in transistors by applying a uniform oxide layer prior to cavity etching

Early embedded silicon germanium with insitu boron doping and oxide/nitride proximity spacer

Enhancing interface characteristics between a channel semiconductor alloy and a gate dielectric by an oxidation process

Methods of epitaxially forming materials on transistor devices

Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor material

Performance enhancement in transistors comprising high-K metal gate stack by reducing a width of offset spacers

Methods of forming isolation structures for semiconductor devices

Reduction of defect rates in PFET transistors comprising a Si/Ge semiconductor material formed by epitaxial growth

Strain engineering in semiconductor devices by using a piezoelectric material

Process flow to reduce hole defects in P-active regions and to reduce across-wafer threshold voltage scatter

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by corner rounding at the top of the gate electrode

Reduction of threshold voltage variation in transistors comprising a channel semiconductor alloy by reducing deposition non-uniformities

Reduced STI topography in high-K metal gate transistors by using a mask after channel semiconductor alloy deposition

Methods of forming a layer of silicon on a layer of silicon/germanium

Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas

Semiconductor element formed in a crystalline substrate material and comprising an embedded in situ doped semiconductor material

Enhancing uniformity of a channel semiconductor alloy by forming STI structures after the growth process

Transistor comprising an embedded semiconductor alloy in drain and source regions extending under the gate electrode

Transistor device comprising an embedded semiconductor alloy having an asymmetric configuration

Transistor with an embedded strain-inducing material having a gradually shaped configuration

Test structure for controlling the incorporation of semiconductor alloys in transistors comprising high-k metal gate electrode structures

Formation of a channel semiconductor alloy by depositing a hard mask for the selective epitaxial growth

Replacement gate process flow for highly scaled semiconductor devices

Reducing contamination in a process flow of forming a channel semiconductor alloy in a semiconductor device

Enhancing deposition uniformity of a channel semiconductor alloy by forming a recess prior to the well implantation

Formation of a channel semiconductor alloy by a nitride hard mask layer and an oxide mask

GLOBALFOUNDRIES INC

Strain engineering in semiconductor devices by using a piezoelectric material

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy

Transistor with embedded Si/Ge material having reduced offset and superior uniformity

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

Reducing contamination in a process flow of forming a channel semiconductor alloy in a semiconductor device

Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules

WASYLUK JOANNA

Methods for PFET fabrication using APM solutions

Methods for pFET fabrication using APM solutions

Horizontal epitaxy furnace for channel SiGe formation

JAVORKA PETER

Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer

Reduced threshold voltage-width dependency and reduced surface topography in transistors comprising high-k metal gate electrode structures by a late carbon incorporation

THEES HANS-JUERGEN

Semiconductor devices comprising a channel semiconductor alloy formed with reduced STI topography

Methods of forming PEET devices with different structures and performance characteristics

FORSCHUNGSZENTRUM JUELICH GMBH

Method for structured application of molecules to a strip conductor and molecular memory matrix

ADVANCED MICRO DEVICES INC

Reduction of thickness variations of a threshold semiconductor alloy by reducing patterning non-uniformities prior to depositing the semiconductor alloy

REICHEL CARSTEN

Enhancing deposition uniformity of a channel semiconductor alloy by an in situ etch process

GLOBALFOUNDARIES INC

Methods of forming a semiconductor device while preventing or reducing loss of active area and/or isolation regions

LENSKI MARKUS

Superior stability of characteristics of transistors having an early formed high-K metal gate

KURZ ANDREAS

Semiconductor device comprising high-k metal gate electrode structures and precision eFuses formed in the active semiconductor material

INTERROLL HOLDING AG

Roller conveyor