Strain engineering in semiconductor devices by using a piezoelectric material

Abstract

An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.

What is claimed: 
     
       1. A semiconductor device, comprising:
 an active region positioned above a substrate; 
 a field effect transistor positioned in and above said active region; 
 a contact structure connecting to said active region, said contract structure defining a direction of current flow through a channel region of said field effect transistor; 
 a buried insulating layer positioned between said substrate and said active region, said buried insulating layer comprising a piezoelectric material layer that is in direct contact with and mechanically coupled to said active region; 
 an isolation structure laterally defining said active region and said buried insulating layer, wherein said buried insulating layer is coextensive with said active region; 
 a first contact connecting to a first contact portion on an upper surface of said piezoelectric material layer; and 
 a second contact connecting to a second contact portion on said upper surface of said piezoelectric material layer, wherein said first and second contact portions of said piezoelectric material layer are positioned so as to define an electric field direction in said piezoelectric material layer that is aligned to said direction of current flow through said channel region of said field effect transistor. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein said first and second contacts are connected to said contact structure. 
     
     
       3. The semiconductor device of  claim 2 , wherein said first contact is connected to a first transistor terminal and said second contact is connected to a second transistor terminal. 
     
     
       4. The semiconductor device of  claim 3 , wherein said first transistor terminal is a drain terminal and said second transistor terminal is a source terminal. 
     
     
       5. The semiconductor device of  claim 1 , wherein said field effect transistor comprises a gate electrode structure positioned above said channel region. 
     
     
       6. The semiconductor device of  claim 5 , wherein a length of said gate electrode structure is approximately 50 nm or less. 
     
     
       7. The semiconductor device of  claim 1 , wherein said active region is a first active region, said field effect transistor is a first field effect transistor, and said buried insulating layer is a first buried insulating layer comprising a first piezoelectric material layer, the semiconductor device further comprising:
 a second active region positioned above said substrate; 
 a second field effect transistor positioned in and above said second active region; 
 a second contact structure connecting to said second active region, said second contract structure defining a direction of current flow through a channel region of said second field effect transistor; 
 a second buried insulating layer positioned between said substrate and said second active region, said second buried insulating layer comprising a second piezoelectric material layer that is in direct contact with and mechanically coupled to said second active region, wherein said second buried insulating layer is coextensive with said second active region, said isolation structure separating and electrically isolating said second active region and said second buried insulating layer from said first active region and said first buried insulating layer; 
 a third contact connecting to a first contact portion on an upper surface of said second piezoelectric material layer; and 
 a fourth contact connecting to a second contact portion on said upper surface of said second piezoelectric material layer, wherein said first and second contact portions of said second piezoelectric material layer are positioned so as to define an electric field direction in said second piezoelectric material layer that is aligned to said direction of current flow through said channel region of said second field effect transistor. 
 
     
     
       8. The semiconductor device of  claim 7 , wherein said first field effect transistor is an N-channel transistor and said second field effect transistor is a P-channel transistor. 
     
     
       9. The semiconductor device of  claim 8 , wherein said first and second contacts and said third and fourth contacts are electrically connected so as to generate oppositely oriented electric fields in said first piezoelectric material layer and said second piezoelectric material layer, respectively. 
     
     
       10. The semiconductor device of  claim 1 , wherein said substrate comprises a crystalline semiconductor material. 
     
     
       11. The semiconductor device of  claim 1 , wherein a thickness of said piezoelectric material layer is approximately 1 μm or less. 
     
     
       12. A semiconductor device, comprising:
 first and second active regions positioned above a substrate, wherein a conductivity type of said first active region is different than a conductivity type of said second active region; 
 a first piezoelectric region positioned between said substrate and said first active region; 
 a second piezoelectric region positioned between said second active region and said substrate; 
 an isolation structure laterally defining said first and second active regions and said first and second piezoelectric regions, wherein said first piezoelectric region is coextensive with said first active region and said second piezoelectric region is coextensive with said second active region; 
 a first transistor element positioned in and above said first active region, said first transistor element comprising a first source region that is electrically coupled to a first upper surface contact portion of said first piezoelectric region positioned below said first source region and a first drain region that is electrically coupled to a second upper surface contact portion of said first piezoelectric region positioned below said first drain region, wherein said first and second upper surface contact portions of said first piezoelectric region are positioned so as to define a first electric field direction in said first piezoelectric region; 
 a second transistor element positioned in and above said second active region, said second transistor element comprising a second source region that is electrically coupled to a first upper surface contact portion of said second piezoelectric region positioned below said second source region and a second drain region that is electrically coupled to a second upper surface contact portion of said second piezoelectric region positioned below said second drain region, wherein said first and second upper surface contact portions of said second piezoelectric region are positioned so as to define a second electric field direction in said second piezoelectric region; 
 a first contact structure connecting to said first active region so as to define a first current flow direction through a channel region of said first transistor element, said first contact structure comprising a first contact connecting to said first source region and a second contact connecting to said first drain region, wherein said first electric field direction is aligned with said first current flow direction; and 
 a second contact structure connecting to said second active region so as to define a second current flow direction through said second transistor element, said second contact structure comprising a third contact connecting to said second source region and a fourth contact connecting to said second drain region, wherein said second electric field direction is aligned with said second current flow direction. 
 
     
     
       13. The semiconductor device of  claim 12 , wherein said first transistor element comprises a first gate electrode structure having a first gate length and said second transistor element comprises a second gate electrode structure having a second gate length, at least one of said first and second gate lengths being less than approximately 50 nm. 
     
     
       14. The semiconductor device of  claim 12 , wherein said first contact structure is configured so as to generate a compressive strain component in said first channel region and said second contact structure is configured so as to generate a tensile strain component in said second channel region. 
     
     
       15. The semiconductor device of  claim 12 , wherein said substrate comprises a crystalline semiconductor material. 
     
     
       16. The semiconductor device of  claim 12 , wherein a thickness of each of said first and second piezoelectric regions is approximately 1 μm or less.