Inventor

KAMMLER THORSTEN

DE63 patents

⚠️ This page may combine multiple inventors who share the name “KAMMLER THORSTEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAMMLER THORSTEN

ADVANCED MICRO DEVICES INC

Circuit element having a metal silicide region thermally stabilized by a barrier diffusion material

Different embedded strain layers in PMOS and NMOS transistors and a method of forming the same

Method of forming a semiconductor device

Embedded strain layer in thin SOI transistors and a method of forming the same

Technique for forming a contact insulation layer with enhanced stress transfer efficiency

Technique for providing multiple stress sources in NMOS and PMOS transistors

Technique for forming recessed strained drain/source regions in NMOS and PMOS transistors

Technique for transferring strain into a semiconductor region

Technique for forming transistors having raised drain and source regions with different heights

Shallow PN junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process

SOI transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same

Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility

Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions

Method of forming a semiconductor device

Method of forming sidewall spacer elements for a circuit element by increasing an etch selectivity

Polysilicon line having a metal silicide region enabling linewidth scaling including forming a second metal silicide region on the substrate

Semiconductor device having a polysilicon line structure with increased metal silicide portions and method for forming the polysilicon line structure of a semiconductor device

Technique for forming a spacer for a line element by using an etch stop layer deposited by a highly directional deposition technique

Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process

Method of determining an orientation of a crystal lattice of a first substrate relative to a crystal lattice of a second substrate

Transistor device having an increased threshold stability without drive current degradation

Method of manufacturing a semiconductor component

Technique for forming recessed sidewall spacers for a polysilicon line

Multi-silicide in integrated circuit technology

Semiconductor component and method of manufacture

Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility

Technique for providing stress sources in MOS transistors in close proximity to a channel region

Technique for forming a substrate having crystalline semiconductor regions of different characteristics located above a crystalline bulk substrate

Method of depositing a layer of a material on a substrate

Technique for forming a transistor having raised drain and source regions with a reduced number of process steps

Method of forming a metal silicide

Field effect transistor having a doped gate electrode with reduced gate depletion and method of forming the transistor

Technique for forming a transistor having raised drain and source regions with a tri-layer hard mask for gate patterning

Conversion of transition metal to silicide through back end processing in integrated circuit technology

Method of forming an epitaxial layer for raised drain and source regions by removing contaminations

Method of forming a field effect transistor

GLOBALFOUNDRIES INC

Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same

Method for reducing crystal defects in transistors with re-grown shallow junctions by appropriately selecting crystalline orientations

Method of forming a gate mask for fabricating a structure of gate lines

Self-aligned silicidation for replacement gate process

Multi-silicide system in integrated circuit technology

WEI ANDY

Method for forming double gate and tri-gate transistors on a bulk substrate

SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto

Method of forming a field effect transistor

KAMMLER THORSTEN

Leakage control in field effect transistors based on an implantation species introduced locally at the STI edge

Using high-k dielectrics as highly selective etch stop materials in semiconductor devices

SEN INDRADEEP

Self-aligned silicidation for replacement gate process

REICHEL CARSTEN

Enhancing deposition uniformity of a channel semiconductor alloy by an in situ etch process

KRONHOLZ STEPHAN

Formation of a channel semiconductor alloy by depositing a hard mask for the selective epitaxial growth

TRENTZSCH MARTIN

Reducing the creation of charge traps at gate dielectrics in MOS transistors by performing a hydrogen treatment