Using high-k dielectrics as highly selective etch stop materials in semiconductor devices

Abstract

A spacer structure in sophisticated semiconductor devices is formed on the basis of a high-k dielectric material, which provides superior etch resistivity compared to conventionally used silicon dioxide liners. Consequently, a reduced thickness of the etch stop material may nevertheless provide superior etch resistivity, thereby reducing negative effects, such as dopant loss in the drain and source extension regions, creating a pronounced surface topography and the like, as are typically associated with conventional spacer material systems.

1. A method, comprising:
 forming a spacer layer stack above a circuit feature formed above an active region of a semiconductor device, said spacer layer stack comprising an etch stop liner and a spacer material formed above said etch stop liner, said etch stop liner comprising a high-k dielectric material; 
 forming a spacer element on sidewalls of said circuit feature by performing a plasma assisted etch process and using said etch stop liner as an etch stop material; and 
 forming a strain-inducing dielectric material above said active region, said circuit feature, and said spacer element in the presence of at least a portion of said etch stop liner. 
 
     
     
       2. The method of  claim 1 , wherein forming said spacer layer stack comprises forming said etch stop liner with a thickness of approximately 10 nm or less. 
     
     
       3. The method of  claim 1 , wherein said etch stop liner comprises at least one of hafnium, tantalum, strontium and zirconium. 
     
     
       4. The method of  claim 3 , wherein said etch stop liner comprises hafnium oxide. 
     
     
       5. The method of  claim 1 , wherein forming said spacer layer stack comprises forming said spacer layer stack above an isolation structure that laterally delineates said active region. 
     
     
       6. The method of  claim 1 , further comprising performing an implantation process and using said spacer element as an implantation mask so as to form a doped region in said active region. 
     
     
       7. The method of  claim 6 , further comprising removing a portion of said etch stop liner that is not covered by said spacer element and forming a metal compound in an exposed portion of said active region. 
     
     
       8. The method of  claim 7 , wherein removing said portion of said etch stop liner comprises performing a wet chemical removal process on the basis of hydrogen and fluorine (HF). 
     
     
       9. The method of  claim 7 , further comprising removing at least a portion of said spacer element after forming said metal compound, wherein said etch stop liner is used as an etch stop material. 
     
     
       10. A method, comprising:
 forming a high-k dielectric material layer above an active region of a transistor so as to cover a gate electrode structure formed at least partially on said active region; 
 forming a spacer layer on said high-k dielectric material layer; 
 forming a spacer element from said spacer layer at sidewalls of said gate electrode structure by performing a plasma assisted etch process and using said high-k dielectric material layer as an etch stop material; and 
 forming a strain-inducing dielectric material above said active region, said circuit feature, and said spacer element in the presence of at least a portion of said etch stop liner. 
 
     
     
       11. The method of  claim 10 , further comprising performing at least one of an etch process and an implantation process and using said spacer element as a mask. 
     
     
       12. The method of  claim 11 , wherein performing an implantation process comprises introducing an implantation species through an exposed portion of said high-k dielectric material. 
     
     
       13. The method of  claim 12 , further comprising removing said exposed portion of said high-k dielectric material after said implantation process by performing at least one of a sputter etch process and a wet chemical etch process. 
     
     
       14. The method of  claim 13 , further comprising forming a metal silicide in an exposed portion of said active region after removing said exposed portion of said high-k dielectric material. 
     
     
       15. The method of  claim 11 , wherein forming a strain-inducing dielectric material further comprising forming the strain-inducing dielectric material after performing said at least one of an etch process and an implantation process. 
     
     
       16. The method of  claim 15 , further comprising removing at least a portion of said spacer element prior to forming said strain-inducing dielectric material by using said high-k dielectric material layer as an etch stop material. 
     
     
       17. The method of  claim 10 , wherein said high-k dielectric material layer comprises at least one of hafnium, tantalum, strontium and zirconium.