Inventor

LENSKI MARKUS

DE57 patents

⚠️ This page may combine multiple inventors who share the name “LENSKI MARKUS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LENSKI MARKUS

GLOBALFOUNDRIES INC

Front-end-of-line device structure and method of forming such a front-end-of-line device structure

Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy

Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer

Method for reducing crystal defects in transistors with re-grown shallow junctions by appropriately selecting crystalline orientations

Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning

Semiconductor device formed by a replacement gate approach based on an early work function metal

Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material

Method for making high-K metal gate electrode structures by separate removal of placeholder materials

Method for selectively forming strain in a transistor by a stress memorization technique without adding additional lithography steps

Blocking pre-amorphization of a gate electrode of a transistor

Transistor having a channel with biaxial strain induced by silicon/germanium in the gate electrode

Work function adjustment in high-K metal gate electrode structures by selectively removing a barrier layer

Method of optimizing sidewall spacer size for silicide proximity with in-situ clean

Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules

Spacer for a gate electrode having tensile stress and a method of forming the same

Method of forming a semiconductor structure including silicided and non-silicided circuit elements

Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

ADVANCED MICRO DEVICES INC

Technique for forming a contact insulation layer with enhanced stress transfer efficiency

Reducing transistor junction capacitance by recessing drain and source regions

Transistor having an asymmetric source/drain and halo implantation region and a method of forming the same

Technique for forming a spacer for a line element by using an etch stop layer deposited by a highly directional deposition technique

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors

Technique for locally adapting transistor characteristics by using advanced laser/flash anneal techniques

Method of forming sidewall spacers

Method for reducing silicide defects by removing contaminants prior to drain/source activation

Method of patterning gate electrodes by reducing sidewall angles of a mask layer

KRONHOLZ STEPHAN

Transistor with embedded Si/Ge material having reduced offset to the channel region

Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor material

Reduced STI topography in high-K metal gate transistors by using a mask after channel semiconductor alloy deposition

Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas

Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules

MOWRY ANTHONY

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backside

Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation

LENSKI MARKUS

Work function adjustment in high-k metal gate electrode structures by selectively removing a barrier layer

Superior stability of characteristics of transistors having an early formed high-K metal gate

GLOBALFOUNDARIES INC

Methods of forming a semiconductor device while preventing or reducing loss of active area and/or isolation regions

KAMMLER THORSTEN

Using high-k dielectrics as highly selective etch stop materials in semiconductor devices

RUELKE HARTMUT

Spacer for a gate electrode having tensile stress and a method of forming the same

RICHTER RALF

Increasing robustness of a dual stress liner approach in a semiconductor device by applying a wet chemistry

FITZ CLEMENS

Methods of forming metal silicide regions on semiconductor devices

FEUDEL THOMAS

Reducing transistor junction capacitance by recessing drain and source regions

METZGER JOACHIM

Enhancing integrity of a high-k gate stack by confining a metal cap layer after deposition