Inventor
WU CHAU-NENG
TW17 patents
⚠️ This page may combine multiple inventors who share the name “WU CHAU-NENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
WINBOND ELECTRONICS CORP
11 patentsUS5631793AMay 20, 1997
Capacitor-couple electrostatic discharge protection circuit
WINBOND ELECTRONICS CORP142 citations98
US5838050ANov 17, 1998
Hexagon CMOS device
WINBOND ELECTRONICS CORP83 citations96
US5721656AFeb 24, 1998
Electrostatc discharge protection network
WINBOND ELECTRONICS CORP66 citations96
US5714784AFeb 3, 1998
Electrostatic discharge protection device
WINBOND ELECTRONICS CORP90 citations96
US5686751ANov 11, 1997
Electrostatic discharge protection circuit triggered by capacitive-coupling
WINBOND ELECTRONICS CORP74 citations96
US5892262AApr 6, 1999
Capacitor-triggered electrostatic discharge protection circuit
WINBOND ELECTRONICS CORP25 citations92
US5777368AJul 7, 1998
Electrostatic discharge protection device and its method of fabrication
WINBOND ELECTRONICS CORP38 citations92
US5670814ASep 23, 1997
Electrostatic discharge protection circuit triggered by well-coupling
WINBOND ELECTRONICS CORP24 citations92
US5892261AApr 6, 1999
SRAM bitline pull-up MOSFET structure for internal circuit electro-static discharge immunity
WINBOND ELECTRONICS CORP17 citations83
USRE38222EAug 19, 2003
Electrostatic discharge protection circuit triggered by capacitive-coupling
WINBOND ELECTRONICS CORP12 citations73
US5777369AJul 7, 1998
Bit-line pull-up circuit or static random access memory (SRAM) devices
WINBOND ELECTRONICS CORP14 citations70
TAIWAN SEMICONDUCTOR MFG
4 patentsUS7274048B2Sep 25, 2007
Substrate based ESD network protection for a flip chip
TAIWAN SEMICONDUCTOR MFG17 citations92
US6407898B1Jun 18, 2002
Protection means for preventing power-on sequence induced latch-up
TAIWAN SEMICONDUCTOR MFG21 citations92
US7362555B2Apr 22, 2008
ESD protection circuit for a mixed-voltage semiconductor device
TAIWAN SEMICONDUCTOR MFG5 citations63
US6849479B2Feb 1, 2005
Substrate based ESD network protection method for flip chip design
TAIWAN SEMICONDUCTOR MFG4 citations62