Electrostatic discharge protection circuit triggered by capacitive-coupling

Abstract

An electrostatic discharge (ESD) protection circuit connected to an integrated circuit pad for protecting an internal circuit from ESD damage. The ESD protection circuit includes an NMOS/PMOS transistor, a capacitor, and a load The NMOS/PMOS is configured with a drain connected to the IC pad and a source for connection to the circuit V SS /V DD . Agate of the NMOS/PMOS transistor is tied to the source. The capacitor is connected between the IC pad and the bulk of the NMOS/PMOS transistor The load, which is either another NMOS/PMOS transistor or a resistor, is to be connected between the V SS /V DD and the bulk of the NMOS/PMOS transistor. In accordance with the invention, the NMOS/PMOS transistor is fabricated in a P-well/N-well region of a semiconductor substrate. The capacitor includes an IC pad and a polysilicon layer therebelow, with an intervening dielectric layer.

What is claimed is:  
     
       1. An electrostatic discharge protection circuit for protecting an internal circuit, comprising: 
       an N-type semiconductor substrate;  
       a P-well region in the substrate;  
       a contact region in the P-well region;  
       an isolating structure on the substrate;  
       a conducting layer on the isolating structure, coupled to the contact region;  
       a dielectric lays overlying the conducting layer;  
       a metal pad on the dielectric layer, wherein the metal pad, the dielectric layer, and the conducting layer form a capacitor for coupling ESD voltage to the P-well region when an ESD stress is present at the pad;  
       a first N-type heavily-doped region in the P-well region, coupled to the pad;  
       a second N-type heavily-doped region for coupling to a circuit ground of the internal circuit, the second N-type heavily doped region being disposed in the P-well region, spaced apart from and electrically isolated from the first N-type heavily-doped region;  
       a gate structure, disposed on the P-well region between the first N-type heavily-doped region and the second N-type heavily-doped region, for connection to the circuit ground, wherein the first N-type heavily-doped region, the second N-type heavily-doped region, the gate structure, and the P-well region form an NMOS transistor which bypasses ESD stress when an ESD voltage is coupled to the P-well region through the capacitor; and  
       a load connected between the contact region and the circuit ground when the gate structure and the second N-type heavily doped region are connected to the circuit ground, for coupling the P-well region of the NMOS transistor to the circuit ground.  
     
     
       2. The electrostatic discharge protection circuit as claimed in  claim 1 , wherein the load is a resistor. 
     
     
       3. The electrostatic discharge protection circuit as claimed in  claim 1 , wherein the load includes means for coupling to a power rail of the internal circuit. 
     
     
       4. The electrostatic discharge protection circuit as claimed in  claim 3 , wherein the NMOS transistor is a first NMOS transistor, and the load is a second NMOS transistor comprising a drain connected to the contact region, a source for connection to the circuit ground, and a gate for connection to the power rail. 
     
     
       5. The electrostatic discharge protection circuit as claimed in  claim 4 , wherein the P-well region is a first P-well region, and further comprising a second P-well region in the semi-conductor substrate. 
     
     
       6. The electrostatic discharge protection circuits, claimed in  claim 5 , wherein the second NMOS transistor is disposed on the second P-well region. 
     
     
       7. The electrostatic discharge protection circuit as claimed in  claim 1 , further comprising a diode having an anode for connection to the circuit ground end a cathode connected to the metal pad. 
     
     
       8. The electrostatic discharge protection circuit as claimed in  claim 4 , wherein the second NMOS transistor further comprises a bulk terminal for coupling to the circuit ground. 
     
     
       9. An electrostatic discharge protection circuit for coupling to a power rail, comprising: 
       a P-type semiconductor substrate;  
       an N-well region in the substrate;  
       a contact region in the N-well region;  
       an isolating someone on the substrate;  
       a conducing layer on the isolating structure, coupled to the contact region;  
       a dielectric layer overlying the conducting layer;  
       a metal pad on the dielectric layer, wherein the metal pad the dielectric layer, and the conducting layer form a capacitor for coupling ESD voltage to the N-well region when an ESD stress is present at the pad;  
       a first P-type heavily-doped region is the N-well region, coupled to the pad;  
       a second P-type heavily-doped region in the N-web region, spaced apart from and electrically isolated from the first P-type heavily-doped region, for coupling to the power rail:  
       a gate structure, formed on the N-well region between the first P-type heavily-doped region and the second P-type heavily-doped region, for correction to the power rail, wherein the first P-type heavily-doped region, the second P-type heavily-doped region, the gate structure, and the N-well region form a PMOS transistor which bypasses ESD stress when an ESD voltage is coupled to the N-well region through the capacitor; and  
       a load connected between the contact region and the power rail when the gate structure is connected to the power rail, for coupling the N-well region of the PMOS transistor to the power rail.  
     
     
       10. The electrostatic discharge protection circuit as claimed in  claim 9 , wherein the load is a resistor. 
     
     
       11. The electrostatic discharge protection circuit as claimed in  claim 9 , wherein the PMOS transistor is a first PMOS transistor and the load is a second PMOS transistor comprising a drain connected to the contact region, a source for connection to the power rail, and a gate for connection to a circuit ground. 
     
     
       12. The electrostatic discharge protection circuit as claimed in  claim 11 , wherein the N-well region is a first N-well region, and further comprising a second N-well region formed in the semiconductor substrate. 
     
     
       13. The electrostatic discharge protection circuit as claimed in  claim 12 , wherein the second PMOS transistor is disposed on the second N-well region. 
     
     
       14. The electrostatic discharge protection circuit as claimed in  claim 9 , further comprising a diode having a cathode for connection to the power rail and an anode connected to the metal pad. 
     
     
       15. The electrostatic discharge protection circuit as claimed is  claim 11 , wherein the second PMOS transistor further comprises a bulk terminal for coupling to the power rail. 
     
     
       16. An electrostatic discharge protection circuit for an integrated circuit, comprising: 
       
         an NMOS transistor having a source terminal, a drain terminal, a gate terminal electrically coupled to a circuit ground, and a bulk terminal;  
       
       
         a capacitor coupled between the bulk terminal and a first node; and  
       
       
         a load coupled between the bulk terminal and a second node, wherein said second node is a power rail and said power rail is V 
         SS  
         bus. 
       
     
     
       17. An electrostatic discharge protection circuit for an integrated circuit, comprising: 
       
         an NMOS transistor having a source terminal a drain terminal a gate terminal electrically coupled to a circuit ground, and a bulk terminal;  
       
       
         a capacitor coupled between the bulk terminal and a fast node; and  
       
       
         a load coupled between the bulk terminal and a second node, wherein said second node is a power rail and said power rail is the circuit ground. 
       
     
     
       18. An electrostatic discharge protection circuit for an integrated circuit, comprising: 
       
         a first MOS transistor having a source terminal, a drain terminal, a gate terminal, and a bulk terminal;  
       
       
         a capacitor coupled between the bulk terminal and a first node; and  
       
       
         a load coupled between the bulk terminal and a second node wherein said load is a second MOS transistor. 
       
     
     
       19. An electrostatic discharge protection circuit for an integrated circuit, comprising: 
       
         a first MOS transistor having a source terminal, a drain terminal, a gate terminal, and a bulk terminal;  
       
       
         a capacitor coupled between the bulk terminal and a first node; and  
       
       
         a load coupled between the bulk terminal and a second node,  
       
       
         wherein said load is a second MOS transistor having a gate, and the gate of said second MOS transistor is coupled to a power rail. 
       
     
     
       20. An electrostatic discharge protection circuit for an integrated circuit, comprising: 
       
         an MOS transistor having a source terminal, a drain terminal, a gate terminal, and a bulk terminal;  
       
       
         a capacitor coupled between the bulk terminal and a first node; and  
       
       
         a load coupled between the bulk terminal and a second node, wherein said gate terminal is coupled to said second node. 
       
     
     
       21. A method of fabricating an integrated circuit with an ESD protection device for protection against ESD stress at a first node by, the method comprising 
       
         forming said ESD protection device of a bulk terminal of a first conductivity type, and first and second diffusion regions of a second conductivity type, wherein said first diffusion region is coupled to the first node and said second diffusion region is coupled to a power rail; and  
       
       
         coupling said bulk terminal to said first node;  
       
       
         wherein the potential of said bulk terminal changes and a forward bias forms between said bulk terminal and said second diffusion region when ESD stress develops at the first node, further comprising coupling said bulk terminal to said power rail;  
       
       
         wherein a potential of the bulk terminal is brought to substantially the same as a potential level of said power rail after a time delay when ESD stress develops at the first node,  
       
       
         wherein said coupling of the bulk terminal to the power rail is made through a load, and  
       
       
         wherein said load is a transistor. 
       
     
     
       22. The method of  claim 21 , wherein said power rail is a first power rail and said transistor load is an MOS transistor having a gate, the method further comprising coupling the gate to a second power rail.