Inventor

RODDER MARK S

US147 patents

⚠️ This page may combine multiple inventors who share the name “RODDER MARK S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RODDER MARK S

TEXAS INSTRUMENTS INC

Methodology for high-performance, high reliability input/output devices and analog-compatible input/output and core devices using core device implants

Process for polycrystalline silicon gates and high-K dielectric compatibility

Transistors with substitutionally formed gate structures and method

Method of forming a MOSFET using a disposable gate and raised source and drain

Method of fabricating a raised source/drain transistor

Shallow-implant elevated source/drain doping from a sidewall dopant source

Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing

Lateral MOSFET having a barrier between the source/drain regions and the channel

Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region

Lateral MOSFET having a barrier between the source/drain regions and the channel region

Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region

Method of forming a MOSFET using a disposable gate with a sidewall dielectric

Semiconductor devices with pocket implant and counter doping

Vertical FET device with low gate to source overlap capacitance

Reduction of hot carrier effects in semiconductor devices by controlled scattering via the intentional introduction of impurities

Method of forming vertical FET device with low gate to source overlap capacitance

Method of fabricating a vertical FET device with low gate to drain overlap capacitance

Raised source/drain transistor

Method of forming silicides having different thicknesses

Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing

Tight pitch gate devices with enlarged contact areas for deep source and drain terminals and method

Method of forming a silicide layer using a pre-amorphization implant which is blocked from source/drain regions by a layer of photoresist

Transistors with independently formed gate structures and method

Semiconductor devices with pocket implant and counter doping

Shallow-implant elevated source/drain doping from a sidewall dopant source

Self-aligned pocket process for deep sub-0.1 μm CMOS devices and the device

Transistor having ultrashallow source and drain junctions with reduced gate overlap and method

Stacked capacitor SRAM cell

Method for forming a stacked semiconductor structure

Process of fabricating elevated source/drain transistor

Method for semiconductor isolation

Stacked capacitor SRAM cell

Trench isolation process with reduced topography

Sub-critical-dimension integrated circuit features

Method for forming a mixed voltage circuit having complementary devices

Method to partially or completely suppress pocket implant in selective circuit elements with no additional mask in a cmos flow where separate masking steps are used for the drain extension implants for the low voltage and high voltage transistors

SAMSUNG ELECTRONICS CO LTD

Gate-all-around nanosheet field-effect transistors and methods of manufacturing the same

Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same

Horizontal nanosheet FETs and method of manufacturing the same

Nanosheet and nanowire devices having source/drain stressors and methods of manufacturing the same

Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same

Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance

Strained stacked nanosheet FETS and/or quantum well stacked nanosheet

Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective width

Thermionically-overdriven tunnel FETs and methods of fabricating the same

Methods of fabricating integrated circuit device with fin transistors having different threshold voltages

Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

OBRADOVIC BORNA J

Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same

Semiconductor devices with structures for suppression of parasitic bipolar effect in stacked nanosheet FETs and methods of fabricating the same

WANG WEI-E

Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods