Self-aligned pocket process for deep sub-0.1 μm CMOS devices and the device

Abstract

A self-aligned pocket process for formation of CMOS devices and the devices by means of a sidewall doped overlayer to achieve deep sub-0.1 μm CMOS with reduced gate length variation. The localized pocket results in reduced C J . The method includes providing a semiconductor substrate and forming a gate electrode over the substrate separated from the substrate by an electrical insulator. A preferably electrically insulating sidewall material which contains a dopant of predetermined conductivity type is formed over and either in contact with or spaced from the sidewalls of the gate electrode. The dopant is caused to migrate into the substrate beneath the sidewall material with some lateral movement to form a pocket of the predetermined conductivity type in the substrate. A further sidewall can be added to the sidewall material after pocket formation. The sidewall material can be later removed. Drain extensions and/or source/drain regions are formed in the substrate of conductivity type opposite the predetermined conductivity type, with or without use of sidewalls as a mask to provide minimal overlap between the drain extensions and/or source/drain regions and the pocket.

What is claim is: 
     
       1. A method of fabricating an integrated circuit, comprising the steps of: providing a semiconductor substrate;   forming a gate structure having a sidewall over said substrate;   forming a first sidewall spacer adjacent said sidewall;   forming drain extension regions of a first conductivity type in said substrate using said first sidewall spacer as a mask;   forming a region of second conductivity type in said substrate extending under said gate structure by: forming a second sidewall spacer adjacent said first sidewall spacer which contains a dopant of said second conductivity type; and   causing said dopant to migrate from said second sidewall spacer to said substrate;     then, forming a third sidewall spacer; and   forming source/drain regions in said substrate using said third spacer as a mask.   
     
     
       2. The method of claim 1, further comprising the step of removing said second sidewall spacer prior to forming said third sidewall spacer. 
     
     
       3. The method of claim 1 wherein said second sidewall spacer is one of a doped electrical insulator and a doped semiconductor material. 
     
     
       4. The method of claim 1 wherein said second sidewall spacer is taken from the class consisting of phosphosilicate glass (PSG), borosilicate glass (BSG) and SiGe.