Inventor

Zhou Huimei

US52 patents

⚠️ This page may combine multiple inventors who share the name “Zhou Huimei”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

Zhou Huimei

IBM

Cutting fins and gates in CMOS devices

Threshold voltage modulation through channel length adjustment

Three-dimensional field effect device

Controlling gate profile by inter-layer dielectric (ILD) nanolaminates

Threshold voltage modulation through channel length adjustment

Three-dimensional field effect device

Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)

Stress modulation of nFET and pFET fin structures

Three-dimensional field effect device

Modulating transistor performance

Nanosheet device with air-gaped source/drain regions

Self-aligned buried power rail cap for semiconductor devices

Three-dimensional field effect device

Nanosheet transistors with self-aligned gate cut

Planar devices with consistent base dielectric

Three-dimensional field effect device

Self-aligned buried power rail cap for semiconductor devices

Three-dimensional field effect device

Stress modulation of nFET and pFET fin structures

Separate gate complementary field-effect transistor

Protection diode to prevent charge damage during MOL

Stacked complementary field effect transistors

Static random access memory device with stacked FETs

Back-end-of-line thin film resistor

Recessed local interconnect formed over self-aligned double diffusion break

Stacked complementary field effect transistors

Layout design for threshold voltage tuning

Anomaly detection using image-based physical characterization

Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)

Differing device characteristics on a single wafer by selective etch

Nanosheet structures having vertically oriented and horizontally stacked nanosheets

Semiconductor device with mitigated local layout effects

Anomaly detection using image-based physical characterization

In-situ chip design for pulse IV self-heating evaluation

Three-dimensional metal-insulator-metal capacitor embedded in seal structure

Semiconductor device with a protective diode connected to a fuse

Co-integrating gate-all-around nanosheet transistors and comb-nanosheet transistors

Semiconductor structure having stacked power rails

Stressed material within gate cut region

Electrostatic discharge diode having dielectric isolation layer

Self-aligned gate contact for VTFETs

Vertical field-effect transistor with T-shaped gate

Fin isolation to mitigate local layout effects

Differing device characteristics on a single wafer by selective etch

Method of fin oxidation by flowable oxide fill and steam anneal to mitigate local layout effects

Threshold voltage modulation through channel length adjustment

Threshold voltage modulation through channel length adjustment

Threshold voltage modulation through channel length adjustment

INT BUSINESS MACHINES CORPORATION

Metal insulator metal capacitor (MIM capacitor)

ELPIS TECH INC

Controlling gate profile by inter-layer dielectric (ILD) nanolaminates