Inventor

BRANNON SHERWOOD

US13 patents

⚠️ This page may combine multiple inventors who share the name “BRANNON SHERWOOD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

9 patents

US5548786AAug 20, 1996

Dynamic bus sizing of DMA transfers

IBM128 citations96

US5544346AAug 6, 1996

System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus

IBM58 citations95

US5313627AMay 17, 1994

Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device

IBM45 citations91

US5673414ASep 30, 1997

Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O device

IBM24 citations91

US5551009AAug 27, 1996

Expandable high performance FIFO design which includes memory cells having respective cell multiplexors

IBM13 citations70

ISHII TAKATOSHI

2 patents

USRE41967ENov 30, 2010

Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator

ISHII TAKATOSHI2 citations61

USRE43235EMar 13, 2012

Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator

ISHII TAKATOSHI1 citations50

NEOMAGIC CORP

1 patent

US6680738B1Jan 20, 2004

Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator

NEOMAGIC CORP41 citations95

CIRRUS LOGIC INC

1 patent

US5748920AMay 5, 1998

Transaction queue in a graphics controller chip

CIRRUS LOGIC INC13 citations71

BRANNON SHERWOOD

IBM

Dynamic bus sizing of DMA transfers

System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus

Parity error detection and recovery

Bidirectional data buffer for a bus-to-bus interface unit in a computer system

Display adapter for virtual VGA support in XGA native mode

Error detection and recovery in a DMA controller

Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device

Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O device

Expandable high performance FIFO design which includes memory cells having respective cell multiplexors

ISHII TAKATOSHI

Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator

Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator

NEOMAGIC CORP

Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator

CIRRUS LOGIC INC

Transaction queue in a graphics controller chip