Inventor · disambiguated record
Robert Brian Likovich, Jr.
Also filed as: LIKOVICH JR ROBERT · LIKOVICH JR ROBERT B · LIKOVICH JR ROBERT BRIAN · LIKOVICH ROBERT B
19 granted patents·3 pending applications·143 citations·filing 2000–2017
93Inventor score
Top patents by PatentIndex Score
22 records- 0187US7246332B2Methods, systems and media for functional simulation of noise and distortion on an I/O busIBM·Filed 2005·Granted Jul 17, 2007·20 cites·20 claims
- 0286US7237210B2Methods, systems and media for managing functional verification of a parameterizable designIBM·Filed 2005·Granted Jun 26, 2007·18 cites·16 claims
- 0381US7089555B2Ordered semaphore management subsystemIBM·Filed 2002·Granted Aug 8, 2006·33 cites·23 claims
- 0472US7143414B2Method and apparatus for locking multiple semaphoresIBM·Filed 2002·Granted Nov 28, 2006·18 cites·10 claims
- 0571US8547760B2Memory access alignment in a double data rate (‘DDR’) systemJENKINS STEVEN K·Filed 2011·Granted Oct 1, 2013·4 cites·8 claims
- 0664US6816829B1System and method to independently verify the execution rate of individual tasks by a device via simulationIBM·Filed 2000·Granted Nov 9, 2004·11 cites·9 claims
- 0763US7398515B2Buckets of commands in a multiprocessor-based verification environmentIBM·Filed 2003·Granted Jul 8, 2008·12 cites·8 claims
- 0863US6876664B1Asynchronous data buffer and a method of use thereofIBM·Filed 2000·Granted Apr 5, 2005·11 cites·14 claims
- 0961US7406690B2Flow lookahead in an ordered semaphore management subsystemIBM·Filed 2002·Granted Jul 29, 2008·7 cites·12 claims
- 1060US8902683B2Memory access alignment in a double data rate (‘DDR’) systemIBM·Filed 2013·Granted Dec 2, 2014·1 cites·8 claims
- 1160US7784002B2Systems for using relative positioning in structures with dynamic rangesIBM·Filed 2008·Granted Aug 24, 2010·2 cites·5 claims
- 1260US7461364B2Methods and readable media for using relative positioning in structures with dynamic rangesIBM·Filed 2006·Granted Dec 2, 2008·2 cites·7 claims
- 1358US7917908B2Flow lookahead in an ordered semaphore management subsystemIBM·Filed 2008·Granted Mar 29, 2011·1 cites·8 claims
- 1452US6643257B1Verifying performance of a buffering and selection network deviceIBM·Filed 2000·Granted Nov 4, 2003·3 cites·10 claims
- 1551US2008162998A1Automatic reconfiguration of an i/o bus to correct for an error bitIBM·Filed 2008·Application pending·0 cites
- 1650US9343123B2Memory access alignment in a double data rate (‘DDR’) systemIBM·Filed 2014·Granted May 17, 2016·0 cites·6 claims
- 1748US9436388B2Memory access alignment in a double data rate (‘DDR’) systemIBM·Filed 2016·Granted Sep 6, 2016·0 cites·11 claims
- 1844US2006182187A1Automatic reconfiguration of an I/O bus to correct for an error bitLIKOVICH ROBERT B JR·Filed 2005·Application pending·0 cites
- 1942US7454753B2Semaphore management subsystem for use with multi-thread processor systemsIBM·Filed 2002·Granted Nov 18, 2008·0 cites·14 claims
- 2042US2019012265A1Providing multi-socket memory coherency using cross-socket snoop filtering in processor-based systemsQUALCOMM INC·Filed 2017·Application pending·0 cites
- 2140US8196111B2Buckets of commands in a multiprocessor-based verification environmentATOJI DAVID M·Filed 2008·Granted Jun 5, 2012·0 cites·12 claims
- 2231US8212588B2Opportunistic bus access latencyHAGGIS THEODORE P·Filed 2010·Granted Jul 3, 2012·0 cites·20 claims
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